JPS63190343A - Formation of insulating film of semiconductor device - Google Patents
Formation of insulating film of semiconductor deviceInfo
- Publication number
- JPS63190343A JPS63190343A JP2189387A JP2189387A JPS63190343A JP S63190343 A JPS63190343 A JP S63190343A JP 2189387 A JP2189387 A JP 2189387A JP 2189387 A JP2189387 A JP 2189387A JP S63190343 A JPS63190343 A JP S63190343A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- radical
- formula
- semiconductor substrate
- desirably
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000011347 resin Substances 0.000 claims abstract description 15
- 229920005989 resin Polymers 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 238000006116 polymerization reaction Methods 0.000 claims abstract description 3
- 239000007788 liquid Substances 0.000 claims description 6
- 125000003545 alkoxy group Chemical group 0.000 claims description 4
- 125000000217 alkyl group Chemical group 0.000 claims description 4
- 125000003118 aryl group Chemical group 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 1
- -1 alkyl radical Chemical class 0.000 abstract description 8
- 238000000576 coating method Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract 2
- CIUQDSCDWFSTQR-UHFFFAOYSA-N [C]1=CC=CC=C1 Chemical compound [C]1=CC=CC=C1 CIUQDSCDWFSTQR-UHFFFAOYSA-N 0.000 abstract 1
- 150000005840 aryl radicals Chemical class 0.000 abstract 1
- 150000003254 radicals Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000002904 solvent Substances 0.000 description 4
- GLCNFQWHPMKFQH-UHFFFAOYSA-N 1,3-dichloro-1,3,2,4-diazadisiletidine Chemical compound ClN1[SiH2]N([SiH2]1)Cl GLCNFQWHPMKFQH-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- PTTPXKJBFFKCEK-UHFFFAOYSA-N 2-Methyl-4-heptanone Chemical compound CC(C)CC(=O)CC(C)C PTTPXKJBFFKCEK-UHFFFAOYSA-N 0.000 description 2
- IAZDPXIOMUYVGZ-UHFFFAOYSA-N Dimethylsulphoxide Chemical compound CS(C)=O IAZDPXIOMUYVGZ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 125000004432 carbon atom Chemical group C* 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- DURPTKYDGMDSBL-UHFFFAOYSA-N 1-butoxybutane Chemical compound CCCCOCCCC DURPTKYDGMDSBL-UHFFFAOYSA-N 0.000 description 1
- POAOYUHQDCAZBD-UHFFFAOYSA-N 2-butoxyethanol Chemical compound CCCCOCCO POAOYUHQDCAZBD-UHFFFAOYSA-N 0.000 description 1
- NQBXSWAWVZHKBZ-UHFFFAOYSA-N 2-butoxyethyl acetate Chemical compound CCCCOCCOC(C)=O NQBXSWAWVZHKBZ-UHFFFAOYSA-N 0.000 description 1
- SVONRAPFKPVNKG-UHFFFAOYSA-N 2-ethoxyethyl acetate Chemical compound CCOCCOC(C)=O SVONRAPFKPVNKG-UHFFFAOYSA-N 0.000 description 1
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 125000005037 alkyl phenyl group Chemical group 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 125000001997 phenyl group Chemical group [H]C1=C([H])C([H])=C(*)C([H])=C1[H] 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
本発明は、半導体装置の絶縁膜形成工程において、凹凸
表面をもつ半導体基板表面上に従来のＣＶＤ法などの無
機膜形成技術で絶縁膜を形成する際生じる絶縁不良等の
問題を解決するため、スピンコード法により成膜可能な
段差被覆性に優れたシリコンオキシナイトライド膜を提
供することにより、従来法の欠点を解決するものである
。[Detailed Description of the Invention] [Summary] The present invention provides a method for forming an insulating film on the surface of a semiconductor substrate having an uneven surface using a conventional inorganic film forming technique such as a CVD method in an insulating film forming process of a semiconductor device. In order to solve problems such as poor insulation, the present invention provides a silicon oxynitride film with excellent step coverage that can be formed by a spin code method, thereby solving the drawbacks of conventional methods.
本発明は半導体装置の絶縁膜形成方法に関し、更に詳し
くは絶縁膜の凹凸や配線段差を平坦化することのできる
半導体装置の絶縁膜形成方法に関する。The present invention relates to a method for forming an insulating film for a semiconductor device, and more particularly to a method for forming an insulating film for a semiconductor device that can flatten unevenness in the insulating film and wiring steps.
大量の情報を高速に処理する方法として情報処理装置の
主体を占める半導体装置は高集積化による大容量化が進
んでおり、ＬＳＩよりも一段と容量の大きなＶＬＳ Ｉ
が実用化されている。Semiconductor devices, which are the mainstay of information processing equipment as a means of processing large amounts of information at high speed, are increasing in capacity due to high integration, and VLSI, which has a much larger capacity than LSI,
has been put into practical use.
ここで、高集積化は単位素子の小形化と高密度化とによ
って行われている。すなわち、配線パターンなどの最小
パターン幅は１μｍ以下のいわゆるサブミクロンにまで
微少化したものが用いられている。Here, high integration is achieved by downsizing and increasing the density of unit elements. That is, the minimum pattern width of a wiring pattern is 1 μm or less, which is so-called submicron.
また、電子回路の集積化は回路パターンの多層化によっ
て行われており、半導体基板上に設けた絶縁層を窓開け
して不純物イオンを拡散させるか或いはイオン注入など
を行って異種の半導体領域を作ると共に、絶縁層上に配
線パターンを形成してそれぞれの領域と回路接続して電
子回路を形成している。In addition, integration of electronic circuits is achieved by multilayering circuit patterns, and by opening windows in the insulating layer provided on the semiconductor substrate to diffuse impurity ions, or by performing ion implantation, different types of semiconductor regions are formed. At the same time, a wiring pattern is formed on the insulating layer and circuit connections are made to each region to form an electronic circuit.
この場合、回路が複雑化してＸ方向パターンとＹ方向パ
ターンとが交差する場合があり、また最近ではかかる電
子回路上に更に半導体層を形成し、これに電子回路を形
成して多層化することも研究されている。In this case, the circuit may become complicated and the X-direction pattern and the Y-direction pattern may intersect, and recently, a semiconductor layer is further formed on the electronic circuit, and an electronic circuit is formed on this to form a multilayer structure. is also being studied.
電子回路がこのように複雑でない場合も配線パターンの
形成による段差の影響は顕著であり、この上に形成する
絶縁層に平坦化作用がなければ、段差部にヒビ割れを生
じたり、またこの上に配線パターンを形成した場合には
断線を生じたりするという問題がある。Even if the electronic circuit is not as complex as this, the effect of the level difference due to the formation of the wiring pattern is significant, and if the insulating layer formed on top of this does not have a planarizing effect, cracks may occur at the level difference, or If a wiring pattern is formed on the substrate, there is a problem that wire breakage may occur.
例えば、被処理基板上に配線パターンを形成し、この上
に絶縁層を形成して絶縁被覆を行う場合に絶縁層は、
■ 絶縁抵抗が高く、耐湿性と耐熱性の優れた材料から
得られるものであること、
■ 基板との接着性が良く、平坦化作用をもっているこ
と、
■ ピンホールやクランクなどの発生のないこと、など
の要件を具備していることが必要である。For example, when forming a wiring pattern on a substrate to be processed and then forming an insulating layer on it to cover it, the insulating layer should be made of a material with high insulation resistance, moisture resistance, and heat resistance. It must meet the following requirements: (1) It must have good adhesion to the substrate and have a flattening effect; (2) It must not generate pinholes or cranks.
すなわち素子の被覆材として使用する場合には耐湿性が
優れており、ピンホールやタラワクなどが無いことが必
要であり、また、多層構造の層間絶縁層として用いる場
合は平坦化作用が優れ、絶縁抵抗が高く、耐熱性がよ（
、ピンホールやクランクのないことが必要である。かか
る絶縁層は、従来、主として化学気相成長法（Ｃｈｅｍ
ｉｃａｌ ＶａｐｏｒＤｅｐｏｓ ｉ ｔｉｏｎ略して
ＣＶＤ法）によってシラン系ガスを用いた無機膜形成技
術が用いられていた。In other words, when used as a covering material for an element, it must have excellent moisture resistance and be free of pinholes and cracks, and when used as an interlayer insulating layer in a multilayer structure, it must have an excellent flattening effect and be an insulating material. High resistance and heat resistance (
, must be free of pinholes and cranks. Conventionally, such insulating layers have been mainly formed by chemical vapor deposition (Chem).
An inorganic film forming technique using a silane-based gas has been used by ical vapor deposition (abbreviated as CVD method).
然し、ＣＶＤ法では段差を無くして平坦化する程度まで
厚く形成することは工程上不可能であった。However, with the CVD method, it is impossible to form a layer thick enough to eliminate steps and flatten the layer due to the process.
前記したように、従来のＣＶＤ法等により、凹凸表面を
有する半導体基板上に、絶縁膜を形成せしめる場合には
、絶縁膜としての必要特性を満足させるために、絶縁膜
をかなりの厚膜としなければならない。しかしながら、
絶縁膜を厚膜とすると、上部配線と下部配線の導通を行
うスルーホール形成工程において、スルーホールが形成
し難くなるという問題があり、しかも絶縁膜を厚膜にし
ても凹凸段差を十分に平坦化することはできなかった。As mentioned above, when an insulating film is formed on a semiconductor substrate with an uneven surface by conventional CVD method, etc., the insulating film must be made quite thick in order to satisfy the required characteristics as an insulating film. There must be. however,
If the insulating film is made thick, there is a problem that it becomes difficult to form through holes in the through hole formation process that connects the upper wiring and the lower wiring.Moreover, even if the insulating film is made thick, it is difficult to sufficiently flatten uneven steps. It was not possible to convert it into
従って、本発明はこのような従来技術の８題点を解決し
て凹凸表面又は段差を有する半導体基板上に平坦な絶縁
膜を形成することのできる半導体装置の絶縁膜形成方法
を提供することを目的とする。Therefore, it is an object of the present invention to provide a method for forming an insulating film for a semiconductor device, which can solve the eight problems of the prior art and form a flat insulating film on a semiconductor substrate having an uneven surface or a step. purpose.
本発明に従えば、前記した問題点は、式（１）（式中、
Ｒは、独立に、アルキル基、好ましくは炭素数１〜６の
アルキル基、アリール基、好ましくはフェニル基若しく
は炭素数１〜４のアルキル基で置換されたアルキルフェ
ニル基又はアルコキシ基好ましくは炭素数１〜４のアル
コキシ基を示し、ｎは重合度、好ましくは１０〜１００
０を示す）で表わされる樹脂液を配線された半導体基板
上に例えばスピンコード法により塗布し、次いで熱処理
することによりシリコンオキシナイトライド絶縁膜を形
成せしめることから成る半導体装置の絶縁膜形成方法が
提供される。According to the present invention, the above problem can be solved by formula (1) (wherein,
R is independently an alkyl group, preferably an alkyl group having 1 to 6 carbon atoms, an aryl group, preferably a phenyl group, or an alkylphenyl group substituted with an alkyl group having 1 to 4 carbon atoms, or an alkoxy group, preferably an alkoxy group 1 to 4 alkoxy groups, n is the degree of polymerization, preferably 10 to 100
A method for forming an insulating film for a semiconductor device comprises applying a resin liquid represented by 0) onto a wired semiconductor substrate by, for example, a spin code method, and then heat-treating to form a silicon oxynitride insulating film. provided.
本発明方法によれば前記した一般式（Ｉ）の樹脂を適当
な溶媒（例えばジイソブチルケトン、ｎ−ブチルエーテ
ル、ブチルセロソルブ、ブチルセロソルブアセテート、
エチルセロソルブアセテートなど）に溶解し、この樹脂
液はスピンコード法などの慣用塗布方法により例えばア
ルミニウム配線を施した半導体基板上に塗布する。塗布
厚は基板表面上の配線厚さく即ち段差や凹凸）にもよる
が、好ましくは１．５〜２．０μｍ（乾燥厚）とする。According to the method of the present invention, the resin of general formula (I) described above is mixed with a suitable solvent (e.g. diisobutyl ketone, n-butyl ether, butyl cellosolve, butyl cellosolve acetate,
(ethyl cellosolve acetate, etc.), and this resin liquid is applied onto a semiconductor substrate provided with aluminum wiring, for example, by a conventional coating method such as a spin-coating method. Although the coating thickness depends on the wiring thickness on the substrate surface (i.e., steps and unevenness), it is preferably 1.5 to 2.0 μm (dry thickness).
なお、前記式（１）の樹脂は例えば下記式のリチウムシ
ランジオレート
■
■
と下記式のジクロロシクロジシラザン
■
とを反応させることにより得ることができる。樹脂の好
ましい重量平均分子量は５．０００〜２００．０００、
分散度（Ｍｉｖ／Ｍｎ）は１．５〜７である。The resin of formula (1) can be obtained, for example, by reacting lithium silanediolate (2) of the following formula with dichlorocyclodisilazane (4) of the following formula. The preferred weight average molecular weight of the resin is 5.000 to 200.000,
The degree of dispersion (Miv/Mn) is 1.5-7.
このようにして樹脂液を塗布した半導体基板を加熱して
溶剤を除去乾燥し、次いで空気又は酸素中で３００〜５
００℃、好ましくは４００〜４５０℃にて熱処理するこ
とにより半導体基板上にシリコンオキシナイトライド（
ＳｉＯＮ）絶縁膜が形成される。The semiconductor substrate coated with the resin liquid in this way is heated to remove the solvent and dried, and then heated to
Silicon oxynitride (
A SiON) insulating film is formed.
本発明に従えば式（Ｉ）で表わされる樹脂を例えばスピ
ンコード法などにより塗布して熱処理することにより、
半導体装置の絶縁膜に用いられているシリコンオキシナ
イトライド膜を半導体基板に形成せしめるため、凹凸表
面を有する基板でもその表面に被覆性・平坦性に優れた
膜を形成することができる。According to the present invention, by applying the resin represented by formula (I) by, for example, a spin code method and heat-treating the resin,
Since the silicon oxynitride film used for the insulating film of semiconductor devices is formed on the semiconductor substrate, a film with excellent coverage and flatness can be formed on the surface of even a substrate having an uneven surface.
以下、実施例に従って本発明を更に、具体的に説明する
が、本発明の技術的範囲をこれらの実施例に限定するも
のでないことはいうまでもない。Hereinafter, the present invention will be explained in more detail with reference to Examples, but it goes without saying that the technical scope of the present invention is not limited to these Examples.
％」−工合迩ＬＵＬＬ
滴下ロート及びジムロート冷却管を備えた四つロフラス
コに、ジメチルスルホキシド溶媒２００ ｇ 。%''-Engineering LULL In a four-necked flask equipped with a dropping funnel and a Dimroth condenser, 200 g of dimethyl sulfoxide solvent.
下記式のリチウムシランジオレ−ト２０ｇＨ３ ＣＨ。Lithium silanediolate 20gH3 of the following formula CH.
及び下記式のジクロロシクロジシラザン２０ｇＨ３
■
Ｃ）１３
を混合した。次に、これにヨウ素１ｇを滴下し、１３０
℃で３時間反応した。and 20 g of dichlorocyclodisilazane of the following formula were mixed. Next, 1 g of iodine was added dropwise to this, and 130
The reaction was carried out at ℃ for 3 hours.
得られたポリマーの重量平均分子量は８．０×１０４、
分散度は２．４であった。The weight average molecular weight of the obtained polymer was 8.0×104,
The degree of dispersion was 2.4.
■）ユ災籐桝と
例１で合成したポリマーをジイソブチルケトンに溶解し
て３０重量％樹脂液を作り、これにアルミニウム（Ｍ）
の配線パターンが施されているＳｉ基板上に回転速度３
０００ｒｐｍで３０秒間スピンコードした。なお、Ｓｉ
基板上の配線パターンは厚さが１μｍ、線幅が１〜１０
０μｍ、線間隔２〜２００μｍであった・
スピンコードした樹脂液は温度１２０℃で３０分間加熱
して溶剤を除去乾燥させ、次に空気中で４５０℃の温度
で１時間加熱して樹脂を硬化させシリコンオキシナイト
ライド膜の、絶縁層を形成した。■) Dissolve Yusai Rattan Masu and the polymer synthesized in Example 1 in diisobutyl ketone to make a 30% by weight resin liquid, and add aluminum (M) to this.
Rotation speed 3 on a Si substrate with a wiring pattern of
Spin code was performed at 000 rpm for 30 seconds. In addition, Si
The wiring pattern on the board has a thickness of 1 μm and a line width of 1 to 10
The spin-coded resin liquid was heated at 120°C for 30 minutes to remove the solvent and dried, and then heated in air at 450°C for 1 hour to harden the resin. An insulating layer of silicon oxynitride film was formed.
このようにして形成した絶縁層について、膜厚を測定し
たところ、配線パターン上では０．８μｍ、配線パター
ン間の凹部では１．７μｍであり、段差は０．１μｍ程
度で平坦化されていた。When the film thickness of the insulating layer thus formed was measured, it was 0.8 μm on the wiring pattern, 1.7 μm in the recess between the wiring patterns, and the thickness was flattened to about 0.1 μm.
また、絶縁層の厚さが１μｍを越すにも拘らず、ピンホ
ールやクランクは全く認められなかった。Further, even though the thickness of the insulating layer exceeded 1 μm, no pinholes or cranks were observed.
次に、２層目の配線を施すために、スルーホールを形成
し、Ｍを蒸着し、２層目のパターニングを行なった。こ
の配線パターン上に上と同様にしてシリコンオキシナイ
トライド膜の絶縁層を形成した。この絶縁膜の表面段差
は０．３μｍ以下であった。Next, in order to provide a second layer of wiring, through holes were formed, M was vapor deposited, and the second layer was patterned. An insulating layer of silicon oxynitride film was formed on this wiring pattern in the same manner as above. The surface level difference of this insulating film was 0.3 μm or less.
以上説明したように、本発明によれば、凹凸表面を有す
る半導体装置に、平坦で信転性の高い、シリコンオキシ
ナイトライド膜を形成することができる。As described above, according to the present invention, a flat silicon oxynitride film with high reliability can be formed on a semiconductor device having an uneven surface.
Claims (1)
ルコキシ基を示し、ｎは重合度を示す）で表わされる樹
脂液を配線された半導体基板上に塗布し、次いで熱処理
することによりシリコンオキシナイトライト絶縁膜を形
成せしめることを特徴とする半導体装置の絶縁膜形成方
法。[Claims] 1. Formula ▲ Numerical formula, chemical formula, table, etc. ▼ (I) (In the formula, R independently represents an alkyl group, aryl group, or alkoxy group, and n represents the degree of polymerization.) 1. A method for forming an insulating film for a semiconductor device, comprising applying a resin liquid represented by the formula above onto a wired semiconductor substrate, and then heat-treating the resin to form a silicon oxynitrite insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2189387A JPS63190343A (en) | 1987-02-03 | 1987-02-03 | Formation of insulating film of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2189387A JPS63190343A (en) | 1987-02-03 | 1987-02-03 | Formation of insulating film of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63190343A true JPS63190343A (en) | 1988-08-05 |
Family
ID=12067782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2189387A Pending JPS63190343A (en) | 1987-02-03 | 1987-02-03 | Formation of insulating film of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63190343A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013038929A1 (en) * | 2011-09-12 | 2013-03-21 | 新日鉄住金化学株式会社 | Organic electroluminescent element material having silicon-containing four membered ring structure, and organic electroluminescent element |
-
1987
- 1987-02-03 JP JP2189387A patent/JPS63190343A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013038929A1 (en) * | 2011-09-12 | 2013-03-21 | 新日鉄住金化学株式会社 | Organic electroluminescent element material having silicon-containing four membered ring structure, and organic electroluminescent element |
| CN103814035A (en) * | 2011-09-12 | 2014-05-21 | 新日铁住金化学株式会社 | Organic electroluminescent element material having silicon-containing four membered ring structure, and organic electroluminescent element |
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