JPS63187072U - - Google Patents
Info
- Publication number
- JPS63187072U JPS63187072U JP7787187U JP7787187U JPS63187072U JP S63187072 U JPS63187072 U JP S63187072U JP 7787187 U JP7787187 U JP 7787187U JP 7787187 U JP7787187 U JP 7787187U JP S63187072 U JPS63187072 U JP S63187072U
- Authority
- JP
- Japan
- Prior art keywords
- testing device
- card
- built
- row
- pin terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005055 memory storage Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 1
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7787187U JPS63187072U (en, 2012) | 1987-05-24 | 1987-05-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7787187U JPS63187072U (en, 2012) | 1987-05-24 | 1987-05-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63187072U true JPS63187072U (en, 2012) | 1988-11-30 |
Family
ID=30926285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7787187U Pending JPS63187072U (en, 2012) | 1987-05-24 | 1987-05-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63187072U (en, 2012) |
-
1987
- 1987-05-24 JP JP7787187U patent/JPS63187072U/ja active Pending