JPS6318594A - Semiconductor device - Google Patents

Abstract

PURPOSE:To set a suitable writing voltage/erasing voltage without applying an excessive electric field stress by providing plural clamp circuits for clamping an output voltage at the time of a writing/erasing mode. CONSTITUTION:There are provided a writing/erasing-reading circuit switching circuit consisting of a boosting circuit LS for boosting the voltage from a power source voltage to a high voltage, the plural clamping circuits 11, 12 disposed for clamping the output of the boosting circuit and a selection circuit for selecting one of the clamping circuits. Since the two clamping circuits 11, 12 are provided, a suitable writing voltage known from the writing characteristic of a memory-cell can be set by the clamp voltage of the other clamp circuit 12. Therefore, the suitable writing voltage and the erasing voltage can be set and accordingly, at the time of the writing or the erasing mode, the excessive electric field stress is not applied to the memory cell.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is an electrically writable and erasable device whose main component is a field effect transistor (hereinafter referred to as ICFET) having an insulated gate structure. The present invention relates to a semiconductor device having a write/erase-read voltage switching circuit built in a non-volatile memory device (hereinafter referred to as EEPROM).

In the conventional EEPROM, the write voltage and erase voltage (usually 20
around V). The write voltage and erase voltage are generally set by a clamp voltage of a clamp circuit built into the chip.

FIG. 6 shows a conventional write/erase-read voltage switching circuit. As the above-mentioned clamp circuit, an example is shown in which the junction breakdown voltage of the N+ diffusion layer on the P substrate is used. Below is the value of junction breakdown voltage BVJ
It is written as

The write/erase-read voltage switching circuit shown in Fig. 6 is a P-channel type in which the source is connected to the power supply CC, the gate is connected to the signal NWE that becomes "L" in write mode and erase mode, and the drain is connected to point A. Enhancement type IC
FET (hereinafter referred to as PE-1CFET) Ml and N whose drain and gate are connected to point A and source is connected to point A.
Channel type enhancement type IGFET <hereinafter NE
-IGFET. ) M2 and a NE-IGFET with the drain and gate connected to the point, and the source connected to the point Pi.
Mpl, NE-IGFET Mp2 whose drain and gate are connected to point Pi and whose source is connected to point P2, and NE-IGFET Mp2 whose drain and gate are connected to point P2 and whose source is connected to point P3.
E-IGFET Mp3..., N whose drain and gate are connected to point P (n-1) and whose source is connected to point Pn
E-IGFET Mpn, NE-IGFET M3 with its drain and gate connected to point Pn, source connected to point C, and NE-IGFET M4 with its drain connected to point C, gate connected to signal NWE, and source connected to ground. A clamp circuit CLA1 that clamps the output voltage during write/erase mode is connected between point Pn and the dot, and a substrate threshold whose drain and gate are commonly connected to the power supply CC and whose source is connected to the dot. IGFET (hereinafter EO-IG
It is written as FET. ) When the write/erase mode ends, M5, the drain, and the gate become “H” for a certain period of time.
NEiGFET M6 whose source is connected to ground, clock φ and point B
capacitance Q Cp 1 connected between clock φ and point P
A capacitor ff1c p2 connected between the clock φ and the point P2, a capacitor Cp3 connected between the clock φ and the point P2, and so on.
゛Capacitor f connected between clock φ and point P(n-1)
f1cpn. The output Vf]p' of the dot is the output of this write/erase-read voltage switching circuit.

The signal DIS is a signal for discharging the charge charged in the capacitor added to the dot during the write/erase mode to the ground when the write/erase mode ends.

Clock φ is an inverted signal of clock φ. clock φ
, the clock φ swings from an output voltage of 0 to a power supply voltage Vcc.

Unless otherwise specified, the PE-ICFET board is powered by C
Assume in C that the substrate of the NE-IGFET is connected to ground.

Also, to simplify the explanation, the threshold values of all PE-rGFETs are the same, and the threshold values are expressed as vtp and NE-ICF.
All ET thresholds are the same, and the threshold is V7N,
The threshold values of all EO-IGFETs are the same, and that threshold value is assumed to be VTO. Furthermore, even when the IGFET is operating with a reverse bias applied between the substrate and the source, the threshold values are simply VTP% ■TN% v
It is written as to.

The operation of the conventional write/erase-read voltage switching circuit will be described with reference to FIGS. 6 and 7.

FIG. 7 shows the voltages of the signal NWE, the signal DIS, and the output Vllll' of the write/erase-read voltage switching circuit when changing from the write mode (time 0 to tl) to the read mode (time t1 to t2). This shows changes over time.

NWE is the time change in the voltage of the signal NWE, D■S is the signal D
The time change of the voltage of IS, VpH'' indicates the time change of the voltage of the output ■pp°, respectively.

Ml , M2 , (Mpl , Cpl), (M p2
, Cp2), (M p3 , Cp3) ,”, (
Mpn, Cpn) constitute an N& charge pump circuit, which boosts the output ρp'' to a high voltage in the write/erase mode. In the read mode, this charge pump circuit is inactive.EO-IGFET M5 is always Since it is connected to conduct, the value of the output vpp' is (V
CC-VT. ].

■When the signal NWE becomes “L” in write mode (time 0 to tl), PE-IGFETMI becomes conductive and NE
Since rGFET M2 is always connected so as to be conductive, the voltage at point B becomes (Vcc-VrN). Here, when the clock φ becomes Vcc, the NE-IGFETM
When pl conducts, the voltage at point B is [: 2 Vcc -VT
)l], and charge is supplied to point P1 through NE-IGFET Mpl.

Next, when the clock φ becomes Vcc and the clock φ becomes 0■, the NE-IC and FET Mp2 become conductive, so that the charge supplied to the point P1 is supplied to the point P2 through the NE-IGFET Mp2.

In this way, charge is supplied to the next stage every half cycle of the clock, and points p1, point P2, ..., point P(n-1)
, Pn, and points with larger subscripts, the charge increases.

At this time, NE-IGFET Mpl, Mp2, Mp3,
. . , Mpn are diode-connected, so there is no reverse flow of charge. In addition, the threshold value of EO-IGFET M5 is designed to prevent charge from flowing back into the power supply CC from the point on, so the voltage of the output VISIT' is [Vcc VT. ] and clamp circuit CLA
It is clamped at a clamp voltage BV of 1. Eventually, the voltage of the output Vpρ° is balanced at the value shown by equation (1).

Vflp″=BV, (1) NE-IGFETM2, M3, Mpl, Mp2,
Mp3,..., Mpn, M6, EO-IGFETM5
Of course, the junction breakdown voltage of is designed to be higher than the clamp voltage BV of the clamp circuit CLAl.

2. During the read mode (time tl - t2) When the write mode ends, the signal DIS is set to "H" for a certain period of time and a λ pulse is applied to the signal DIS, so that the NEiGFET M6 becomes conductive. Then, the charge charged in the capacitance added at the time of write mode is discharged with a time constant determined by the current drive capability of NE-IGFET M6 and the value of the capacitance added to the dot, and the voltage at the dot becomes CVCC-V. a. ].

As mentioned above, in the write/erase mode, the write/erase-read voltage switching circuit operates and the output V
The value of flll' becomes a value BVJ limited by the clamp voltage of the clamp circuit. This voltage is the write voltage,
or erase voltage, and the memory cell selected by the address is written or erased.

How many volts to set the clamp voltage of the clamp circuit depends on the EEFROM write speed standard, erase speed standard, write speed characteristics of the memory cell when process parameters vary, erase speed characteristics, withstand voltage of the memory cell, etc. It is determined.

Generally, in an EEPROM, the writing or erasing speed varies greatly depending on the value of the writing voltage or the erasing voltage determined by the clamp voltage of the clamp circuit. for example,
It is assumed that the writing speed is 1 ms when the clamp voltage of the clamp circuit is set so that BVJ = 21 V.

Here, if you reset the clamp voltage of the clamp circuit so that BVJ = 20■, the writing speed will increase to 1Q.
It becomes ms.

Therefore, in EEPROM, it is essential to evaluate the write speed characteristics of the memory cell when the write voltage changes and the erase speed characteristics of the memory cell when the erase voltage changes in the product.

For this reason, when using a conventional write/erase-read voltage switching circuit, a test mode is generally provided, and in addition to the write voltage and erase voltage generated by the booster circuit inside the chip, the write voltage directly from the external terminal, An erase voltage was applied, and the write speed characteristics of the memory cell when the write voltage changed, and the erase speed characteristics of the memory cell when the erase voltage changed were evaluated.

Furthermore, depending on the structure of the memory cell, erasing of the memory cell may be sufficient with a voltage lower than the value of the write voltage. In this case, if the erase voltage is set to the same value as the write voltage as in the conventional example, excessive electric field stress will be applied to the memory cell during the erase mode, shortening the life of the memory cell.

Problems to be Solved by the Invention As described above, the conventional write/erase-read voltage switching circuit has only one clamp circuit that clamps the output voltage during the write/erase mode, so the following problems can be solved. A problem arises.

1. Since the write voltage and erase voltage are set to the same value, for example, if erasing can be performed with a voltage lower than the clamp voltage of the clamp circuit, excessive electric field stress may be applied to the memory cell during erase mode. Become. This shortens the life of the memo IJ-cell.

2. To evaluate the write speed characteristics of the memory cell when the write voltage changes and the erase speed characteristics of the memory cell when the erase voltage changes, apply the write voltage and erase voltage directly from the external terminal during test mode. This necessity complicates the logic circuitry within the EEPROM.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, to enable the write voltage and erase voltage to be set to different values inside the chip, and to improve the write speed characteristics of the memory cell and the erase voltage when the write voltage changes. To provide a semiconductor device having a write/erase-read voltage switching circuit that eliminates the need to apply write voltage and erase voltage directly from an external terminal in order to evaluate the erase speed characteristics of a memory cell when the voltage changes. It is in.

Means for Solving the Problems The semiconductor device of the present invention includes a booster circuit that boosts the power supply voltage to a high voltage, a plurality of clamp circuits provided for clamping the output of the booster circuit, and a plurality of clamp circuits provided for clamping the output of the booster circuit. The write/erase-read voltage switching circuit includes a selection circuit for selecting one of the clamp circuits.

Example FIG. 1 shows a first embodiment of the present invention.

The first embodiment shown in FIG. 1 adds an NE-IGFET Mcl whose drain is connected to point Pn, gate to signal Tp, and source to point E to the conventional circuit shown in FIG. A parasitic transistor (hereinafter simply referred to as a parasitic transistor) Mc2 (hereinafter simply referred to as a parasitic transistor) whose gate is commonly connected to point E and whose source is connected to ground and uses the element isolation region as a channel.
Hereinafter, the threshold value of the parasitic transistor will be referred to as VT2. ), the source and substrate are connected to the output vpp' of the write/erase-read voltage switching circuit, the gate is connected to point G, Drain is point F
PE-IGFET MLl connected to , the drain is connected to point F, and the gate is connected to the signal T that becomes “H” in erase mode.
NE-IGFET ML2 whose source is connected to ground;
PE-IGFET ML3 whose source and substrate are connected to Vlllp, gate connected to point F, and drain connected to point G; NE-IGFET ML4 whose drain is connected to point G, gate connected to point H, and source connected to ground; is connected to the voltage #CC, the gate is connected to the signal T, and the drain is connected to the point H.
GFET ML5, drain connected to point H, gate connected to signal T
NE-IGFET ML6 with source connected to ground
and a level shifter circuit LS.

In FIG. 1, the same parts as those in FIG. 6 of the conventional example are given the same reference numerals and explanations will be omitted. The circuit operations of the charge pump circuit in the write/erase mode and in the read mode are exactly the same as in the conventional example, and therefore the description thereof will be omitted.

Figure 2 shows the output of the write/erase-read voltage switching circuit when the write mode is first entered, then the read mode ends, then the erase mode is entered again, and then the read mode is entered. NWE is the time change of the voltage of the signal NWE,
DIS represents a time change in the voltage of the signal DIS, T represents a time change in the voltage of the signal T, Tp represents a time change in the voltage of the level shifter circuit LS, and ■ρp° represents a time change in the voltage of the output vpp'.

The operation of the first embodiment will be explained using FIGS. 1 and 2. Parasitic transistor 9 of second clamp circuit CLA12
MC2 (DVr2) value is [BVJ - VT)1]
Let's proceed with the discussion assuming the following settings. For example, BVJ
=25V, the value of VT2 of the parasitic transistor Mc2 is set to 20V.

■In write mode (time 0-tl) signal NWE is “
When the voltage becomes "L" and the write mode is entered, the charge pump circuit operates.Then, the output vpp' of the write/erase-read voltage switching circuit rises from (Vcc-Va.).In the write mode, the signal T is " Therefore, the output Tp becomes "L", and as a result, NE-IGFET Mcl of the second clamp circuit CLΔ12 becomes non-conductive.

Therefore, since the second clamp circuit CLA12 is not selected, the voltage of the output vpp' is changed to that of the first clamp circuit CLAI.
It is limited by the junction breakdown voltage of I. Eventually the output
The voltage of ρp° is balanced at the value shown by equation (2).

Vpp' = BVJ = Vpρ(BVJ)...(2
) At this time, the drain breakdown voltage of NE-IGFETMcl is higher than the junction breakdown voltage of the clamp circuit CLAII (of course, it is set).

2. In the read mode (time t1-t2-t3) When the write mode ends, the signal NWE becomes "H",
The charge pump circuit becomes inactive. So the signal DIS
Since a pulse that becomes “H” for a certain period of time is applied to
The charges charged in the capacitor added to the output vpp' during the write mode are discharged. Eventually, the voltage of the output vpp' is balanced at (Vcc-Vto).

3. In erase mode (time t3 to t4) signal NWE is “
When the signal T becomes "H" and the erase mode is activated, the charge pump circuit operates again.Then, the voltage of the output vpp' of the write/erase-read voltage switching circuit rises from CVCC-Vd o). .

At this time, since the signal T is "H", the voltage of the output Tp of the level shifter circuit LS rises together with the output VISIT', and the NE-IGFET Mcl becomes conductive. When the voltage at point E reaches the value of the preset clamp voltage, the parasitic transistor M c 2 becomes conductive. The clamp voltage of the second clamp circuit CLA12 is CBVJ VTI
Since it is set to be less than IE, the output V[)
The voltage at p' is limited by the clamp voltage (Vt2) of the second clamp circuit CLA12. Eventually the output V
The voltage of pρ' is balanced at the value shown in equation (3).

Vl)I)” = Vl2 + Vt+v = Vpp(
Vt□) ... (3) 4° readout mode (time t4
~t5) When the erase mode ends, the signal NWE becomes “H”.
” and the charge pump circuit becomes inactive again.

At this time, a pulse that becomes "H" for a certain period of time is applied to the signal DIS, so that the charge stored in the capacitor added to the output vpp' during the erase mode is discharged.

As a result, the voltage of the output vpp' is balanced at (Vcc-Vt.).

As described above, since the circuit of the first embodiment of the present invention includes two clamp circuits, the appropriate write voltage known from the write characteristics of the memory cell is set by the clamp voltage of one clamp circuit. However, an appropriate erase voltage known from the erase characteristics of the memory cell can be set using the clamp voltage of the other clamp circuit. Therefore, more appropriate write voltages and erase voltages can be set than in the conventional example. Therefore, excessive electric field stress is not applied to the memory cell during write or erase mode.

FIG. 3 shows a second embodiment of the invention.

The second embodiment shown in FIG. 3 adds an NE-IGFET Mc3 whose drain is connected to point Pn, gate to signal Tpl, and source to point E1 to the conventional circuit shown in FIG. A parasitic transistor Mc4 (L threshold is Vt2 (
1)) A second clamp circuit CLΔ22 consisting of
and NE-IGFET Mc5 whose drain is connected to the point Pn, whose gate is connected to the signal Tp2, and whose source is connected to the point E2,
A parasitic transistor MC6 (threshold value V T 2 (
2) A third clamp circuit CLA2 consisting of
PE-, whose source is connected to the power supply CC, whose gate is connected to the signal S for selecting the clamp circuit, and whose drain is connected to point 11.
IGFETMkll, the source is connected to the power supply CC, the gate is connected to the signal T that becomes “H” in erase mode, and the drain is connected to the point I.
PE-IGFET Mk12 connected to point t, NE-IGFET Mk13 whose drain is connected to point It, gate to signal S, source to point J1, and drain connected to point J.
NE-IGFET Mk14 whose gate is connected to signal T and source to ground, and PE- whose source is connected to power supply CC, gate is connected to point 1, and drain is connected to point 1.
IGFET Mk15, NE-IC, F with the drain connected to point 1, the gate connected to point 1, and the source connected to ground.
A first clamp circuit selection circuit composed of ETMk16, a level shifter circuit LS whose human power is connected to point 1 and whose output is connected to point G1, whose source is connected to the power supply CC and whose gate is connected to the inverted signal S of the signal S. , PE-IGFET Mk21 whose drain is connected to point 2, and PE- whose source is connected to power supply CC, gate is connected to signal T, and drain is connected to point I2.
IGFET Mk22 and NE-ICFE with drain connected to point I2, gate to signal S, and source to point J2
TMk23 and NE-IGFET Mk24 with drain connected to point J2, gate connected to signal T, and source connected to ground.
and PE-IGFET Mk25 whose source is connected to the power supply CC, gate to point I2, and drain to point 2, and NE- whose drain is connected to point 2, gate to point I2, and source to ground. IGFET Mk26 and human power 2
and a second clamp circuit selection circuit comprising a level shifter circuit LS whose output is connected to point G2.

The level shifter circuit denoted by LS has exactly the same circuit configuration as the level shifter circuit LS shown in FIG.

Components in FIG. 3 that are the same as those in the conventional example shown in FIG. 6 are given the same reference numerals and explanations will be omitted.

In FIG. 4, the erase mode is first entered, and the second clamp circuit C
LA22 is selected, then the read mode ends,
Next, the erase mode is entered again, this time the third clamp circuit CLA23 is selected, and the read mode is entered. It shows the time change of the voltage of the output Tp1 of the clamp circuit selection circuit and the time change of the voltage of the output Tp2 of the second clamp circuit selection circuit.

NWE is the time change in the voltage of the signal NWE, DIS is the time change in the voltage of the signal DIS, T is the time change in the voltage of the signal T, S is the time change in the voltage of the signal S, and S is the voltage of the signal S. , Tpl represents a time change in the voltage of the output Tpl of the first clamp circuit selection circuit, and Ta2 represents a time change in the voltage of the output Tp2 of the second clamp circuit selection circuit.

The operation of the second embodiment will be explained using FIGS. 3 and 4.

Parasitic transistor Mc of second clamp circuit CLA22
The value V T 2 (1) of ■□ in 4 is (BVJ −V
t2) and the third clamp circuit CLA23 is set below.
The value of vτ2 of the parasitic transistor Mc6 v t 2 (
2) is ■A.

We will proceed with the discussion assuming that it is set even smaller than (1).For example, when lf, BVJ = 25V, vtz (1)
C is set to 20V, and ■1□(2) is set to 18V.

1. During erase mode (time 0 to tl) When the signal NWE becomes "L" and the signal T becomes "H" and the erase mode is entered, the charge pump circuit operates.Then, the output of the write/erase-read voltage switching circuit VpI
The voltage of T' increases from [Vcc-VTa3. At this time, since the signal S is "H" and the signal S is "L",
The second clamp circuit selection circuit becomes non-selected. Also, since the output Tp2 becomes "L", the third clamp circuit CL
NE-IGFET Mc5 of A23 becomes non-conductive. On the other hand, the first clamp circuit selection circuit is selected and the output Tpl
The voltage increases with the output vpp'. Then, NE-IGFET Mc3 of the second clamp circuit CL A22 becomes conductive. When the voltage at point E1 becomes equal to the set clamp voltage value, parasitic transistor Mc4 becomes conductive. The clamp voltage of the second clamp circuit CLA22 is (BV
Since it is set to be less than J -Vt5),
The voltage of the output Vi)p' is the voltage of the second clamp circuit CLA2.
2 clamp voltage (Vt2(1)). Eventually, the voltage of the output Vllll)' is balanced at the value shown by equation (4).

Vpl)' -Vt2(1)+VTN-vpp (V
t2(1)) ' (4) At this time, NE-IGFETM
It goes without saying that the drain breakdown voltages of c3 and Mc5 are set higher than the junction breakdown voltage of the first clamp circuit.

2. In the read mode (time 1 to t2 to t3) When the erase mode ends, the signal NWE becomes "H" and the charge pump circuit becomes inactive. Therefore, a pulse that becomes "H" for a certain period of time is applied to the signal DIS, so that the charge stored in the capacitor added to the output VISIT' during the erase mode is discharged. In the end, the voltage of the output Vl)I)″ is r
(2) Equilibrate at (c-Vto).

Also, at time t1, the signal S is “L” and the signal S is “H”.
Therefore, the first clamp circuit selection circuit becomes non-selected. Therefore, the voltage of the output Tpl becomes "L", and the second clamp circuit selection circuit is selected. Eventually, the voltage of the output Tp2 is balanced at (VCC-VTOI).

3. In erase mode (time t3 to t4) signal NWE is '
When the signal T becomes "L" and the signal becomes "H", and the erase mode is entered, the charge pump circuit operates again. Then, the voltage of the output Vlll] of the write/erase-read voltage switching circuit rises from (Vcc-Vto). At this time, since the signal S is "L" and the signal S is "H", The clamp circuit selection circuit No. 1 becomes unselected. Also, the output Tp
Since l becomes "L", the second clamp circuit CLA22
NE-IGFET MC3 becomes non-conductive. On the other hand, the second
The third clamp circuit selection circuit is selected, and the voltage of the output Tp2 rises with the output vpp', and the third clamp circuit CL
NE-IGFET Mc5 of A23 is conductive. When the voltage at point E2 becomes equal to the set clamp voltage value, parasitic transistor Mc6 becomes conductive. The clamp voltage of the third clamp circuit CLA23 is set to be less than or equal to [BVJ VTNI, so the voltage of the output vpp' is the clamp voltage of the third clamp circuit CLA23 (v↑2 (2)) It will be restricted. Eventually, the voltage of the output vpp' is balanced at the value shown by equation (5).

Vpp' = Vt□ (2) + V7v = vpp (
VT2 (2)) ... (5) 4. In the read mode (time t4 to t5) When the erase mode ends, the signal NWE
becomes "H", and the charge pump circuit becomes inactive again.

At this time, a pulse that becomes "H" for a certain period of time is applied to the signal DIS, so that the charge charged in the capacitor added to the output Vl)11' during the erase mode is discharged.

As a result, the voltage of the output Vllfl” is (Vcc-Vto)
Equilibrium at . Further, at time t4, the signal S becomes "H" and the signal S becomes "L", so that the first clamp circuit selection circuit is selected. Therefore, the voltage of output Tpl is CVcc-VT
Equilibrate at O). In this case, the second clamp circuit selection circuit becomes non-selected, and the voltage of the output Tp2 becomes "L'".

FIG. 5 shows that in the erase mode when the circuit of the second embodiment shown in FIG. 3 is used, the signal S is set to "H" and the signal S is set to L, and the second clamp circuit CLA22 is selected. The output vpp” of the write/erase-read voltage switching circuit is
pp (VT2(1))), the threshold value of the erased memory cell ゛ with respect to the erase time. (E
) (curve P), signal S is “L”, signal S is “H”
”, select the third clamp circuit CLA23, and set the output of the blue fill/erase-read voltage switching circuit Vl)I
)' is set to vpp (VT2(2)) ), the threshold value of the erased memory cell against the erase time ■Th(
It shows the change in E) (curve Q).

In the case of this example, the erase speed characteristics of the memory cell when the erase voltage changes can be evaluated using FIG. This can be used to further determine the clamp voltage of the clamp circuit.

As described above, in the second embodiment of the present invention, in the erase mode, the erase voltage can take two types of values, so the erase voltage can be applied without directly applying the erase voltage from the external terminal.
It is possible to evaluate the erase speed characteristics of memory cells when changing the erase voltage. Therefore, there is an advantage that the logic circuit inside the chip is simpler than in the case of the conventional example.

Effects of the Invention As described above, the write/erase-read voltage switching circuit of the present invention includes a plurality of clamp circuits that clamp the output voltage in the write/erase mode, so it has the following advantages. be.

1. The optimal write voltage can be set based on the write characteristics of the memory cell, and the optimal erase voltage can also be set based on the erase characteristics of the memory cell. Write voltage/erase voltage can be set.

, 2. It is possible to evaluate the write speed characteristics/erase speed characteristics of a memory cell when changing the write voltage/erase voltage without applying the write voltage/erase voltage directly from an external terminal. The circuit becomes simpler.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIG. 2 is a level shifter circuit when changing from write mode to erase mode when the circuit of the embodiment of FIG. 1 is used. Time change of voltage of output Tp and write/erase -
3 is a circuit diagram showing the second embodiment of the present invention, and FIG. 4 is a circuit diagram showing the second embodiment of the present invention. Temporal changes in the voltages of output Tpl and Tp2, write/erase-read voltage when the second clamp circuit CLA22 is selected and when the third clamp circuit CLA23 is selected in the erase mode using the circuit shown in FIG. It shows the change over time in the voltage of the output Vl)I)' of the switching circuit, and Fig. 5 shows the change in the erased memory cell when the erasing time changes when the circuit shown in Fig. 3 is used. This is an example of measuring the change in threshold value. Figure 6 shows a conventional write/erase-read voltage switching circuit, and Figure 7 shows the change from write mode to read mode when using the conventional example. This figure shows the time change in the voltage of the output vpp' of the write/erase-read voltage switching circuit when the voltage changes. (Main reference numbers) Ml, M2, (Mpl, ・Cpl), (M p2
, Cp2), (Mp3,'Cp3),・
...(Mpn, Cpn)...Charge pump circuit that operates in write/erase mode, CLAII...A charge pump circuit that uses a junction breakdown voltage to clamp the voltage of output vpp' in write/erase mode, CLA12...Output vpp' LS... Level shifter circuit, CL A22, CL A23... Clamp circuit that clamps the voltage of output VPP' in write/erase mode, CLA 1... Clamp circuit using junction breakdown voltage. Patent Applicant NEC Corporation - Figure 1 CLA12 Ward Call q Figure 7

Claims (1)

[Claims] In the write/erase-read voltage switching circuit, the write/erase-read voltage switching circuit includes a booster circuit that boosts the power supply voltage to a high voltage, and one clamp circuit that clamps the output of the booster circuit. A semiconductor device further comprising one or more clamp circuits and a selection circuit for selecting one of the plurality of clamp circuits.