JPS6318585A - Muting controller - Google Patents

Abstract

PURPOSE:To prevent unnecessary muting by selecting an error signal corresponding to one rotating head when the other rotating head produces a blinding and varying a counted value according to the error signal at the time of reproducing the rotating head producing no blinding. CONSTITUTION:An up down counter means consisting of ahead decision circuit 2, a control circuit 21, an adder 50 and a latch circuit 51 is provided and a data selector 40 selects a constant defined to be twice from terminals A0-A7 when one bit of mode signals MODE goes to an H level to instruct an interleave recording. In a mode for instructing an interleaved recording, a muting control signal according to the error signal at the time of reproducing the rotating head producing no blinding of the first and the second rotating heads is produced. At the time of reproducing an interleave recorded magnetic tape, even when the one rotating head produces the blinding, if the other rotating head can normally reproduce, the unnecessary muting can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a muting control device, and more particularly to a muting control device that controls muting in response to an error signal indicating the presence or absence of an error in each data block of a digital audio signal. Regarding a control device.

2. Description of the Related Art Recently, a rotary head digital audio tape recorder (rR-DAT) has been developed which digitizes audio signals, records them on magnetic tape using a rotary head, and plays them back.
J) has been developed.

The R-DAT described above sequentially encodes the samples obtained by sampling an analog audio signal every predetermined number of samples to generate a digital audio signal, and converts this digital audio signal into a first . Each of the second rotary heads records 128 data blocks on one track of the magnetic tape.

Furthermore, among the above samples, the odd numbered sample sampled at the odd numbered number and the even numbered sample sampled at the even numbered number are separated, and, for example, the digital audio signal of the odd numbered sample is recorded with the first rotating head, and the digital audio signal of the even numbered sample is recorded. Interleave recording is also performed in which digital audio signals are recorded with a second rotating head.

Moreover, R-DAT is the above-mentioned No. 1. The digital audio signal reproduced from the magnetic tape by the second rotary head is checked for errors for each data block.

As a result, the data block with an error has an H level,
Figure 2 (A) of L level with error-free data block
An error signal ERR as shown in FIG. 2(B) is generated, and a count pulse CP of one pulse as shown in FIG. 2(B) is generated for each data block.

Even if some data blocks of the digital audio signal are erroneous, the noise generated in the converted analog audio signal is temporary and does not cause any auditory problems when the analog signal is played.

Therefore, the error rate of the digital audio signal is measured, and if there is a problem, the analog audio signal is muted.

Problems to be Solved by the Invention If the gab of a rotary head becomes clogged with dirt or the like, the digital audio signal that the rotary head reproduces from the magnetic tape will drop out.

For example, when muting is performed with an error rate of 50% or more, even if the first rotating head performs almost normal playback with an error rate of 10%, the second rotating head becomes clogged and playback cannot be performed with an error rate of 100%. In this case, the error rate of the reproduced digital audio signal is 55%, and muting becomes difficult.

By the way, if the magnetic tape is interleaved and the first rotary head is normally playing back as described above, all the odd tracks, that is, the odd samples will be played back, so the interpolation of the odd samples will be By doing this, it is possible to obtain an approximate analog audio signal, so there is no need to perform muting, and the conventional 8-position system has a problem in that muting is performed unnecessarily.

The present invention provides a selection instruction means, an up/down counter means,
It is an object of the present invention to provide a muting control device that solves the above problems by using count value control means and signal generation means.

Means for Solving the Problems In the present invention, the selection indicating means selects the first m ( (m is a natural number where m<N) When it is specified that all the data blocks have errors, the second rotary head selects and instructs the error signal corresponding to the N-m data blocks to be reproduced, and the first rotary head N data blocks played by the first rotary head when at least one data block of the first m data blocks played by
- select and instruct error signals corresponding to m data blocks and instruct non-interleaved recording, select and instruct error signals corresponding to N data blocks to be reproduced by each of the first and second rotary heads;

The up/down counter means counts down or counts up according to the error signal selected and instructed by the selection instruction means, and when the error rate of the digital audio signal is a predetermined value, the count value is approximately constant at an arbitrary value. Become.

The count value control means makes each value of the down count and up count of the up/down counter means twice in a mode instructing interleaved recording than in a mode instructing non-interleaved recording.

The signal generation means instructs to stop (or start) muting when the count value of the up-down counter means reaches a predetermined first value by up-counting,
When the count value becomes a predetermined second value smaller than the first value due to down-counting, a muting control signal is generated that instructs to start (or stop) muting.

In the present invention, when one of the first and second rotary heads becomes clogged in a mode that instructs interleaved recording, an error signal corresponding to the other rotary head is selected to prevent the clog. Muting control is performed by varying the count value in response to an error signal during playback of a rotary head that is not activated, and furthermore, the count value is varied by approximately 1/2 of the mode that instructs non-interleaved recording. In a mode instructing a certain interleaved recording, each value of up-count or down-count is doubled and muting t, 1JIIl is performed.

Embodiment FIG. 1 shows a block system diagram of an embodiment of the apparatus of the present invention. In the figure, an error signal ERR shown in FIG. 2(A) is input to the terminal 1a, a count pulse CP shown in FIG. 2(B) is input to the terminal 1b, and a plurality of bits are input to the terminal 1C. Configuration mode signals MODE are input, and these signals are supplied to the head determination circuit 2. Note that the above mode signal MO
DE is a signal that indicates the presence or absence of interleaved recording and the error rate to be set, and is sent to the R-DAT controller (
(not shown).

Further, a frame pulse FLP shown in FIG. 3(A) comes into the terminal 1d, a field pulse FIP shown in FIG. 3(8) comes into the terminal 1e, and a field pulse FIP shown in FIG. C
) are input, and these are supplied to the head determination circuit 2. The above signals FLP, FI
P and FLC are each supplied from the R-DAT controller, frame pulse FLP is a signal that instructs the first rotary head to start reproducing every rotation of the first and second rotary heads, and the feed pulse FIP is the first. This is a signal that instructs each of the second rotary heads to start reproduction, and the frame clock FLC is a signal that instructs each of the second rotary heads to start reproduction. For switching each of the second rotary heads (No. 3), the above signals FLP, F
The reproduced digital audio signal of the first rotary head for each of IP and FLC is the part f shown in 8 of FIG. 3(D),
The reproduced digital audio signal of the second rotary head is the part shown in B. In each part of A and B, see Figure 2 (8).
) 128 count pulses CP are generated.

The head determination circuit 2, which is the selection instruction means, has a configuration shown in FIG. In the figure, counter 3 is field pulse FI
When P is supplied to the clear terminal CLR, the terminal QA=Qo
Clear the count value of 4 pits to zero.

The fourth bit of the above count value is output from terminal Qo,
It is inverted by the inverter 4 and supplied to the AND circuit 5, and the AND circuit 5 receives the field pulse FIP after inputting it.
Count pulse CP passes 8 pulses and counter 3
The clock input terminal of the JK type 7 lip-flop is supplied to the clock input terminal of the JK type 7 lip-flop. Also, AND circuit 7
outputs 120 count pulses excluding the above 8 pulses.

The flip 70 knob 6 has the J input terminal supplied with an error signal inverted by the inverter 8, and the σ output terminal connected to the input terminal, and the flip 70 knob 6 supplies the frame pulse FLP to the clear terminal CLR. is supplied and cleared, the level of the J input terminal is latched by the output count pulse of the AND circuit 5. Therefore, the first 8 of the digital audio signals reproduced by the first rotary head are
If there is even one data block without an error, the QE terminal goes to H level, and if all eight data blocks have errors, the Q terminal goes to L level. The Q terminal output of the flip 70 knob 6 is a head selection signal that selects the first rotary head at H level and the second rotary head at H level, and the first 8 data of the first rotary head. When all blocks have errors, it is determined that the first rotary head is clogged.

The Q terminal output of the flip-flop 6, that is, the head selection signal is supplied to an AND circuit 10, and is also supplied to an inverter 11.
The signal is inverted and supplied to the AND circuit 12. Further, the AND circuit 10 is supplied with the frame clock FLC inverted by the inverter 13 and the output count pulse of the AND circuit 7, and the AND circuit 12 is supplied with the frame clock FLC.
The output count pulses of the LC and AND circuit 7 are respectively supplied. Therefore, the AND circuit 10 outputs a count pulse of 120 pulses when reproducing the rotary head in box 1 when the head selection signal is at H level, and the AND circuit 12 outputs a count pulse of 120 pulses when reproducing the rotary head in box 2 when the head selection signal is at L level. It outputs a count pulse of 120 pulses at a time.

The selected count pulses output from the AND circuits 10 and 12 are passed through the OR circuit 14 to the data selector 1.
It is supplied to terminal a of 5. All count pulses CP are supplied to the terminals of the data selector 15 from the terminal 1b. The data selector 15 takes out the selected count pulse from terminal a when one bit of the mode signal MODE is at H level to instruct interleaved recording, and takes out the selected count pulse from terminal a when it is at L level to instruct not to perform interleaved recording. All count pulses CP of
is selected and output from terminal 16.

The operation of the head determination circuit 2 described above is shown in FIG. Detection of the first eight data blocks is performed (step 61).
. It is determined whether or not all of the first eight blocks have errors (step 62), and if there is no error in even one block, the remaining 120 count pulses are selected and output during the first rotary head reproduction (step 63). )
, if all of them are errors, 120 count pulses are selected and output except for the first 8 pulses during the second rotary head reproduction (step 64). Also, if it is not interleaved recording, the first. All count pulses CP are output during reproduction of each of the second rotary heads (step 65).

The error rate control circuit 21 shown in FIG. 1 has a configuration shown in FIG. 6. In the figure, 23 is a constant generator, and for example, the values are 1 (=v00000001') and 2 (='00001') in 8 bits.
OO00koOv).

-1 (='1111 1111'), -2 (='111
1 1110') and -4 (='11111100') are generated. The above angle is a two's complement number. A constant with a value of 1 is supplied to terminals a and b of the data selector 24, and a constant with a value of 2 is supplied to a terminal C of the data selector 24. The constants for the values -2゜-4 and -1 are data selector 2.
5 are supplied to terminals a, b, and c, respectively.

For example, two bits of the mode signal are supplied to the data selector 24.25.
5 each outputs the value coming into terminal a when this mode signal indicates the first mode, outputs the constant coming into terminal a when in the second mode, and outputs the constant coming into terminal C when in the third mode. Output the constant that comes. Constants output from each of the data selectors 24 and 25 are supplied to terminals a and b of the data selector 26, respectively. The data selector 26 outputs from the terminal 27 the constant from the data selector 24 which is input to the terminal a when the error signal is a torque signal, and is input to the terminal a when the error signal is a torque signal. The constant from the data selector 25 is output from the terminal 27. - The 8-bit constant output from the terminal 27 is supplied to the gate circuit 30 shown in the first diagram. The gate circuit 30 and the gate &111111 circuit 31 have the configuration shown in FIG. In the figure, an error signal and a minimum value instruction signal min are input from a terminal 33a to an AND circuit 32 in a gate υ1111 circuit 31, and an error signal inverted by an inverter 35 and a maximum value instruction signal are input to an AND circuit 34. A signal max is received. The instruction signals min and max are signals generated by the decoder 52 when the output count value of the latch circuit 51, which will be described later, reaches a predetermined value. The NOR circuit 36 determines the torque level from the output signals of the AND circuits 32 and 34 when the minimum value instruction signal is Torbel and the error signal is 1 level, and when the maximum value instruction signal is Torbel and the error signal is Torbel. A gate signal is generated and supplied to each of, for example, eight AND circuits 37a to 37h forming the gate circuit 30.

The AND circuits 37a to 3711 have terminals 38a to 38, respectively.
Each bit of the 8-bit constant output from the control circuit 21 is supplied from each of the AND circuits 37a to 37h, and each bit of the 8-bit constant is supplied to the terminals 39a to 39b only when the gate signal is a torque signal. When the gate signal is a trubel, all bits are set as 907 and supplied to the data selector 40 as shown in FIG.

The data selector 40 has a configuration as shown in FIG. In the figure, the first to eighth bits of the constant output from the gate circuit 30 are input to the terminals 418 to 41h, and the data selector 4
0 terminals 80 to 87, respectively. Also, the first constant
The ~7th bit is supplied to each of the terminals A1 to A7 of the data selector 40, and the @7 bit is supplied to the terminal AO of the data selector 40.
701, that is, the trubel signal is supplied from -41i.

Therefore, the constant output from the gate circuit 30 is supplied as is to the terminals 80 to B7 of the data selector 40, and the terminal AO
-A7 is supplied with a constant that is shifted to the left by one bit, that is, doubled.

The data selector 40 selects a constant that is twice that of terminals AO to A7 when 1 bit of the mode signal @MODE indicates interleaved recording at trubel, and selects a constant that is twice the terminal from terminals AO to A7 when 1 bit of the mode signal @MODE indicates interleaved recording at trubel. Select a constant from BO~87, select the constant 8
The bits are supplied from the terminals YO to Y7 to the terminal a of the tensioner 50 via the terminals 42a to 42h.

The adder 50 adds the values supplied to the terminals a and b, and supplies the resulting value to the latch circuit 51 in, for example, 8 bits.

The latch circuit 51 is supplied with the count pulse output from the head determination circuit 2, and latches the output value of the adder i50 at the rising edge of this count pulse. It is supplied to the terminal of the fraud device 30. The control circuit 21, adder 50, and latch circuit 51 described above constitute up/down counter means.

The decoder 52 has a count value set to a preset minimum value MI.
When the count value is less than or equal to N, the minimum value instruction signal min is generated, and the mute-on value MUTE ON is set in advance.
(>MIN), generates a mute-on signal MON, and mute-off value MU whose count value is set in advance
When TE 0FF (>MUTE ON), a mute off signal MOFF is generated, and when the count value is greater than a preset maximum value MAX (>MUTE 0FF), a maximum value instruction signal @max is generated, and the instruction signal min.

max respectively to the goo 81111111 circuit 31,
Mute on signal (MON>, mute off signal (MO
FF) are supplied to a JK type flip-flop 54.

Here, set the minimum direct MIN and mute/liMUTE settings to set the time from the start of playback to the start of output of B voice to the desired value.
OFF (ml value) is [? and set the maximum value MAX and mute on value MUTE ON (second control) to set the time from the end of playback to the audio output path r to the desired value.
The mute off value MUTE is set to have hysteresis to eliminate unstable operation during playback.
OFF and a mute-on value MtJTEON are set, and the decoder 52 is set to the first mode in response to two bits of the mode signal from the terminal 1C.

Minimum value MIN and maximum value M in 2nd mode and 3rd mode respectively
AX, mute on value MUTE ON, mute off lit! MLITE OFF is set variably.

The mute-on signal MO'N and mute-off signal MOFF output from the decoder 52 are respectively supplied to the J input terminal of a JK type flip-flop 54. The count pulse output from the head determination circuit 2 is supplied to the input terminal of the flip-flop [1 block 54].
The flip-flop 54 generates a muting control signal for instructing muting, and outputs it from a terminal 55. In other words, the decoder 52 and the 7-lip flop 54
constitutes a signal generation means.

Here, in the first mode, the terminal a of the addition B30 has the following information:
When the error signal is a trubel, a constant of value -2 is supplied;
A constant of value 1 is provided for trubel. In other words, the absolute values of positive constants and negative constants are unrelated. Therefore, the count value output from the terminal 33 is the ratio of 2 data blocks without error to 1 data block with error, that is, the error rate is 3.
It becomes approximately constant at 3.3%.

Similarly, in the second mode, the error signal is Torbel (
or Torbel), a constant of -4 (or 1) is supplied, and the count value output from terminal 33 has an error rate of 20.
%, it is approximately constant.

Similarly, in the third mode, the error signal is Torbel (
or torque), a constant of Jti-1 (or 2) is supplied, and the count value output from the terminal 33 becomes approximately constant when the error rate is 66.7%.

For example, in the second mode, the error rate is 2 after starting playback.
If it is less than 0%, the count value increases as shown in Figure 9, and when it exceeds the MUTE OFF value, muting v
The l all signal becomes a torque signal and a sound is output.

Thereafter, when the count value reaches the maximum value, up-counting of the count value is stopped and only down-counting is performed.

When the error rate exceeds 20%, the count value decreases. Further, when the error rate is 20%, the count value is constant at an arbitrary value. Actually, the value is close to the maximum value MΔX. Furthermore, when the error rate exceeds 20%, the count value decreases, and when it becomes less than the mute-on value MLITE ON, the muting t, ++a signals become torbel, and the output of audio is stopped. After this, the count value is the minimum [M
When IN, down-counting of the count value is stopped and only up-counting is performed. After this, the above operation is continued depending on the change in the error rate. In this case, if the error rate is 20%, the count value will hardly change /v,
The smaller the error rate, the greater the upward slope to the right;
The greater the error rate, the greater the downward slope to the right. Similar operations are performed in the first mode and the third mode, but in the first mode.

The error rate was 33.3% and 66.
At 7%, the count value hardly changes.

In this way, since the count value changes according to the error rate, appropriate muting υ is performed depending on the noise m generated in the analog audio signal converted from the digital audio signal.
can be controlled.

Also, minimum value MIN, mute off value MUTE OFF
(first value), maximum fIiMAX, mute-on value MU
By setting TE ON (second value), it is possible to set the simultaneous start and end times of audio output to the desired values, and to provide stable audio output by adding hysteresis characteristics. Obtainable.

Furthermore, when reproducing an interleaved recording magnetic tape, if the first rotary head is not clogged, the count pulses of 120 pulses during reproduction of the first rotary head are supplied to each of the latch circuit 51, the flip 70, and the knob 54. The error signal ERR at this time is selected and the up/down counter is activated, and the up/down counter is not activated during reproduction by the second rotary head. In addition, if the first rotating head is clogged, the latch circuit 51 and the flip-flop 5
A count pulse of 120 pulses during reproduction of the second rotary head is supplied to each of the four rotary heads, and the error signal ERR at this time is
is selected and the up/down counter is activated.

In other words, the first. When the second rotary head is not clogged, the 7-up down counter is activated and its count value changes. Therefore, even if the second rotary head becomes clogged, if the error rate of the digital audio signal reproduced by the first rotary head is low, the muting Ullll signal output from the terminal 55 will remain at the L level, and the muting is not carried out.

In addition, in the case of interleaved recording, the up/down counter operates only when the first or second rotary head is reproducing, but at this time, the data selector 40 supplies a double constant to the adder 50, which is not interleaved recording. In this case, the up/down counters operate together during reproduction of the first and second rotary heads, and at this time the data selector 40 supplies the constant to the adder 50 as is.

Therefore, regardless of whether or not interleaved recording is performed, the amount of change in the count value of the up/down counter per unit time is approximately the same, and muting is on.

The time required to control muting off is approximately the same.

Note that it is not necessarily necessary to vary the value to be counted up and the value to be counted down depending on the first to third modes. Further, in the above embodiment, the count value was explained as being 8 bits, but it is needless to say that the count value is not limited to this.

Effects of the Invention As mentioned above, the muting control device according to the present invention has the following advantages:
Selection instruction means, up/down counter means, and count W
Since it consists of a 1tIllD means and a signal generation means, muting is performed in response to an error signal during playback of the non-clogged rotary head of the first and second rotary heads in a mode that instructs interleaved recording. If a v control signal is generated and the other rotating head can perform normal playback even if one rotating head becomes clogged during playback of an interleaved magnetic tape, unnecessary muting can be prevented, and interleaving can be further improved. In both the mode that instructs interleaved recording and the mode that instructs non-interleaved recording, the change in count value per unit time is the same, and the time required to control muting on and muting off is the same. It has certain features such as:

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the apparatus of the present invention; FIGS. 2 and 3 are waveform diagrams of signals input to the apparatus shown in FIG. 1; FIGS. 4 and 6; 7 and 8 are circuit configuration diagrams of each part of the device shown in FIG. 1, FIG. 5 is a flow chart for explaining the operation of the circuit shown in FIG. 4, and FIG. 9 is for explaining the operation of the device of the present invention. This is the cause of 2... Head determination circuit, 3... Counter, 6.54
゜67...Flip-flop, 15.40...Data selector, 21...Error rate v control circuit, 23...
・Constant generator, 30...Gate circuit, 31...Gate a, II 111 circuit, 50...Adder, 51...
-Latch circuit, 52...decoder. Patent Applicant: Victor Company of Japan Co., Ltd. No. 2 - Ichiyu Fig. 5 Fig. 6 21

Claims (1)

[Claims] A digital audio signal encoded in units of data blocks has N (N is a natural number) data blocks in one track, and the digital audio signals of odd-numbered tracks and even-numbered tracks are interleaved or non-interleaved. Each track of the recorded magnetic tape is sequentially scanned by the first and second rotary heads to indicate the presence or absence of an error in each data block of the reproduced digital audio signal when the digital audio signal is reproduced. In a muting control device that uses an error signal to generate a muting control signal, the error signal causes the first of N data blocks to be reproduced by the first rotary head in a mode indicating interleaved recording. When it is specified that all m (m is a natural number where m<N) data blocks have errors, select and instruct error signals corresponding to N-m data blocks to be reproduced by the second rotary head, and At least one of the first m data blocks played by one rotary head
When it is indicated that the data block has no errors, the corresponding first
A mode that selects and instructs error signals corresponding to N-m data blocks to be reproduced by the first and second rotary heads, and instructs non-interleaved recording, corresponding to N data blocks to be reproduced by the first and second rotary heads, respectively. selection instructing means for selecting and instructing an error signal to be selected; and counting down or up in accordance with the error signal selected and instructing by the selection instructing means, and when the error rate of the digital audio signal is a predetermined value, a count value is determined. up-down counter means whose values are approximately constant at an arbitrary value; and two modes in which the down-count and up-count values of the up-down counter means are set in a mode in which the interleaved recording is instructed and in a mode in which the non-interleaved recording is instructed. a count value control means for doubling the count value; and an instruction to stop (or start) muting when the count value of the up-down counter means reaches a predetermined first value by up-counting, and the count value is decreased. It is characterized by comprising a signal generating means for generating a muting control signal that instructs to start (or stop) muting when the count reaches a predetermined second value smaller than the first value. Muting control device.