JPS63182768A - Identifying system for rising method of processor - Google Patents
Identifying system for rising method of processorInfo
- Publication number
- JPS63182768A JPS63182768A JP1334287A JP1334287A JPS63182768A JP S63182768 A JPS63182768 A JP S63182768A JP 1334287 A JP1334287 A JP 1334287A JP 1334287 A JP1334287 A JP 1334287A JP S63182768 A JPS63182768 A JP S63182768A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- configuration information
- processors
- storage device
- startup
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 230000000630 rising effect Effects 0.000 title abstract 6
- 238000010586 diagram Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はプロセッサの立ち上げ方法識別方式に関し、特
に疎結合マルチプロセッサシステムにおけるプロセッサ
の立ち上げ方法識別方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for identifying a startup method for a processor, and more particularly to a method for identifying a startup method for a processor in a loosely coupled multiprocessor system.
従来、疎結合マルチプロセラサシステムラ立チ上げる場
合、立ち上げ前に立ち上げモードスイッチを設定したり
、立ち上げ中にコンソールから立ち上げ方法を指示した
iする等の入手介入が必要であった。Conventionally, when starting up a loosely coupled multi-processor system, it was necessary to set the startup mode switch before startup, or to obtain instructions on how to start up from the console during startup. .
上述した従来の技術は人手介入を必要とするため操作性
が悪く、′fた。立ち上げ方法の指定ミスによiシステ
ムが立ち上がらず、または、幾つかのプロセッサが切シ
離されてしまうという問題点があった。The above-mentioned conventional techniques require manual intervention and have poor operability. There was a problem in that the i-system did not start up or some processors were disconnected due to an error in specifying the startup method.
本発明は従来のもののこのような問題点を解決するため
に、各プロセッサの立ち上げ方法を人手の介入を必要と
せず自動的に識別する方式を提供することを目的とする
。SUMMARY OF THE INVENTION In order to solve these problems of the conventional technology, it is an object of the present invention to provide a method for automatically identifying the startup method of each processor without requiring manual intervention.
本発明によると、他プロセッサの運用状態を監視するマ
スクプロセッサを有する疎結合マルチプロセッサシステ
ムにおいて、各プロセッサは構成情報格納装置に接続さ
れ、前記構成情報格納装置にマスクプロセッサからプロ
セッサ構成情報を書き込む手段と、前記構成情報格納装
置よりプロセッサ、構成情報を各プロセッサに読む手段
とを有し。According to the present invention, in a loosely coupled multiprocessor system having a mask processor that monitors the operational status of other processors, each processor is connected to a configuration information storage device, and means for writing processor configuration information from the mask processor to the configuration information storage device. and means for reading processor and configuration information from the configuration information storage device to each processor.
各プロセッサは立ち上げ時に前記構成情報格納装置から
プロセッサ構成情報を読み、プロセッサ構成情報の内容
によシ自プロセッサの立ち上げが通常立ち上げか組み込
み立ち上げかを判断し、マスタプロセッサはシステム全
体の立ち上げ後及びプロセッサの構成変更時にプロセッ
サ構成情報を前記構成情報格納装置に書き込むことを特
徴とするプロセッサの立ち上げ方法識別方式が得られる
。At startup, each processor reads the processor configuration information from the configuration information storage device, and depending on the contents of the processor configuration information, determines whether the startup of its own processor is a normal startup or an embedded startup. A processor startup method identification method is obtained, which is characterized in that processor configuration information is written into the configuration information storage device after startup and when the processor configuration is changed.
〔実施例〕 次に9本発明について図面を参照して説明する。〔Example〕 Next, nine aspects of the present invention will be described with reference to the drawings.
第1図は本発明を適用する装置の一実施例のブロック構
成図である。図中、lは構成情報格納装置、10は疎結
合マルチプロセッサシステムである。この疎結合マルチ
!ロセッサシステムlo内の20〜20nはプロセッサ
であシ、そのうちマスタゾロセッサ20はプロセッサ2
1〜2nの運用状態を監視する。
1いずれのプロセッサ20〜2nもそれぞれ構成情
報格納装置1に接続される。FIG. 1 is a block diagram of an embodiment of an apparatus to which the present invention is applied. In the figure, 1 is a configuration information storage device, and 10 is a loosely coupled multiprocessor system. This loosely coupled multi! 20 to 20n in the processor system lo are processors, of which the master processor 20 is the processor 2.
Monitor the operational status of 1 to 2n.
1. Each of the processors 20 to 2n is connected to the configuration information storage device 1.
第2図は構成情報格納装置l内のプロセッサ構成情報の
一例である。図中、 co % cnはプロセラプロセ
ッサ20〜2nは、それぞれ立ち上げ時に、自グロセッ
サの立ち上げが全体を同時に立ち上げる通常立ち上げか
、他プロセッサが運用中の組み込み立ち上げかを調べる
ため、構成情報格納装置1からプロセッサ構成情報を読
む。FIG. 2 is an example of processor configuration information in the configuration information storage device l. In the figure, co % cn indicates the configuration of the processor processors 20 to 2n, in order to check whether the startup of the own processor is a normal startup in which all processors are started at the same time, or an embedded startup when other processors are in operation. Read processor configuration information from the information storage device 1.
もしプロセッサ構成情報が初期状態ならば全体を同時に
立ち上げるものとみなし通常立ち上げを行なう。プロセ
ッサ構成情報が初期状態でなければ、運用状態d欄の自
プロセッサの識別子に対する部分を参照し、自プロセッ
サが切シ離されていれば組み込み立ち上げを行ない、自
プロセッサが運用中ならば通常立ち上げを行なう。If the processor configuration information is in the initial state, it is assumed that all the processors will be started up at the same time, and normal startup will be performed. If the processor configuration information is not in the initial state, refer to the part corresponding to the identifier of the own processor in the operation status d column, and if the own processor is disconnected, start up the built-in process, or if the own processor is in operation, start up normally. Do a raise.
マスタプロセッサ20は、全体を同時に立ち上げる通常
立ち上げ後、立ち上がったプロセッサを運用中、立ち上
がらなかったプロセッサを切シ離し状態としてプロセッ
サ構成情報を作成し、構成情報格納装置1に書き込む。After a normal startup in which all processors are started up simultaneously, the master processor 20 creates processor configuration information by placing the processors that have started up in operation, disconnects the processors that have not started up, and writes them into the configuration information storage device 1.
またマスタゾロセッサ20はあるプロセッサがダウンし
て切シ離されたり、あるプロセッサが組み込まれたシし
て構成状態が変化すると、それに基づい゛てプロセッサ
構成情報を作成し、構成情報格納装置1に書き込む。In addition, when a certain processor goes down and is disconnected, or a certain processor is installed and the configuration state changes, the master processor 20 creates processor configuration information based on it and stores it in the configuration information storage device 1. Write.
構成情報格納装置1は、プロセッサ20〜2nに指示さ
れると、指示をしたプロセッサにプロセッサ構成情報を
送る。また構成情報格納装置1はマスタプロセッサ20
からプロセッサ構成情報を受けると、それまで保存して
いたプロセッサ構成情報を新しいプロセッサ構成情報に
置き換え、常に最新のプロセッサ構成情報を保存する。When instructed by the processors 20 to 2n, the configuration information storage device 1 sends the processor configuration information to the processor that gave the instruction. Further, the configuration information storage device 1 is a master processor 20
When processor configuration information is received from , the previously saved processor configuration information is replaced with new processor configuration information, and the latest processor configuration information is always saved.
以上説明したように9本発明は疎結合マルチプロセッサ
システムにおける各プロセッサの立ち上げ方法を人手の
介入を必要とせず自動的に識別できる効果がある。As explained above, the present invention has the effect of automatically identifying how to start up each processor in a loosely coupled multiprocessor system without requiring manual intervention.
第1図は本発明を採用した装置の一実施例のブロック構
成図、第2図は第1図における構成情報格納装置内のプ
ロセッサ構成情報の一例を示す図である。
記号の説明:1は構成情報格納装置、10は疎結合マル
チプロセッサシステム、20はマスタゾれあられしてい
る。
第1図
第2図
Go−Cn:ブロ’r、−m別子
d:″M用状豫を示す欄
1°運用中
2:切離し中FIG. 1 is a block diagram of an embodiment of a device employing the present invention, and FIG. 2 is a diagram showing an example of processor configuration information in the configuration information storage device in FIG. 1. Explanation of symbols: 1 is a configuration information storage device, 10 is a loosely coupled multiprocessor system, and 20 is a master system. Fig. 1 Fig. 2 Go-Cn: Bro'r, -m Separate d: ″M Column showing the status 1° In operation 2: Disconnected
Claims (1)
サを有する疎結合マルチプロセッサシステムにおいて、
各プロセッサは構成情報格納装置に接続され、該構成情
報格納装置にマスタプロセッサからプロセッサ構成情報
を書き込む手段と、前記構成情報格納装置よりプロセッ
サ構成情報を各プロセッサに読む手段とを有し、各プロ
セッサは立ち上げ時に前記構成情報格納装置からプロセ
ッサ構成情報を読み、プロセッサ構成情報の内容により
自プロセッサの立ち上げが通常立ち上げか組み込み立ち
上げかを判断し、マスタプロセッサはシステム全体の立
ち上げ後及びプロセッサの構成変更時にプロセッサ構成
情報を前記構成情報格納装置に書き込むことを特徴とす
る、プロセッサの立ち上げ方法識別方式。1. In a loosely coupled multiprocessor system that has a master processor that monitors the operational status of other processors,
Each processor is connected to a configuration information storage device, and has means for writing processor configuration information from a master processor into the configuration information storage device, and means for reading processor configuration information from the configuration information storage device to each processor, and each processor reads the processor configuration information from the configuration information storage device at startup, and determines whether the startup of its own processor is a normal startup or an embedded startup based on the contents of the processor configuration information. A method for identifying a method for starting up a processor, characterized in that processor configuration information is written into the configuration information storage device when changing the configuration of the processor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1334287A JPS63182768A (en) | 1987-01-24 | 1987-01-24 | Identifying system for rising method of processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1334287A JPS63182768A (en) | 1987-01-24 | 1987-01-24 | Identifying system for rising method of processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63182768A true JPS63182768A (en) | 1988-07-28 |
Family
ID=11830446
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1334287A Pending JPS63182768A (en) | 1987-01-24 | 1987-01-24 | Identifying system for rising method of processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63182768A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09218862A (en) * | 1996-02-14 | 1997-08-19 | Nec Corp | Multiprocessor system |
JP2005352677A (en) * | 2004-06-09 | 2005-12-22 | Sony Corp | Multiprocessor system |
US7356686B2 (en) | 2003-06-02 | 2008-04-08 | Nec Corporation | Initialization of range registers within chipsets on spare processor cells |
-
1987
- 1987-01-24 JP JP1334287A patent/JPS63182768A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09218862A (en) * | 1996-02-14 | 1997-08-19 | Nec Corp | Multiprocessor system |
US7356686B2 (en) | 2003-06-02 | 2008-04-08 | Nec Corporation | Initialization of range registers within chipsets on spare processor cells |
JP2005352677A (en) * | 2004-06-09 | 2005-12-22 | Sony Corp | Multiprocessor system |
JP4525188B2 (en) * | 2004-06-09 | 2010-08-18 | ソニー株式会社 | Multiprocessor system |
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