JPS63181194A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To minimize the upscale of a hardware and to transfer the data without burdening a software by providing a path connecting directly with the data lines of EEPROM and the data lines of RAM and by providing a means for controlling the direct transfer of the data between them. CONSTITUTION:The EEPROM array 11 and the RAM array 21 have a common column address to connect the data lines of the EEPROM array 11 with the data lines of RAM array 21 by a direct connecting path 85 through a switch 84. The control circuit for the transfer is actuated by the soft ware and controls the operation of address resistors 81, 82, a switch 84, etc. The switch 84 is turned on by this control signal. The read signal is supplied to the EEPROM array 11 and the write signal is supplied to RAM array 21 to effect the concurrent transfer from a designated load address of the EEPROM array 11 to a designated load address of the RAM array 21. Hence, the burden of the soft ware is mitigated and the upscale of hard ware is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to semiconductor integrated circuit technology, and relates to a technology that is effective when applied to a single-chip microcomputer incorporating an electrically writable nonvolatile memory.

[Conventional technology] EEPROM (Electrical-ly Er
Asable and programmable
An example of a single-chip microcomputer with a built-in memory (read only memory) is "Hitachi Hyoron," Vol. 68, No. 7, pages 29 to 32, published by Hitachi Hyoronsha on July 25, 1986. EEP
The time required for writing to ROM is faster than the CPU (Central
ral Processing Unit), which is about 10' to 10' times faster. Therefore, the CPU could not directly process the data stored in the EEPROM. Therefore, the data stored in EEPROM is temporarily stored in RAM (Random Ac
cess memory), and after being subjected to predetermined processing by the CPU, it was written to the EEPROM. For example, EEP R that allows page writing
In OM, data for one page is prepared and then transferred one byte at a time from RAM to EEPROM.
It is a good idea to transfer it to . Furthermore, since there is a limit to the number of times the EEPROM can be rewritten, only the final results are written to the EEPROM as much as possible.

[Problems to be solved by the invention] However, from EEF ROM to RAM,
Transfer of data from M to EEFROM had to be done by the CPU. Therefore, there was an inconvenience that a burden was placed on the software. This burden can be reduced by incorporating a DMA controller, but this would increase the scale of the hardware.

On the other hand, a memory device has been proposed that combines the high speed of RAM and the nonvolatility of EEFROM by combining a nonvolatile memory element and a RAM cell. February 1, 1983
rISSCCDigest of Te published on the 3rd
chnical PapergJ pages 170-17
(See page 1). However, according to this method, since cells with different structures are combined, there is a problem in that the area of the storage device becomes considerably larger than the sum of the areas of the RAM and the EEPROM. Therefore, such a memory device is particularly inappropriate for being built into a relatively small-scale semiconductor integrated circuit device such as a single-chip microcomputer.

An object of the present invention is to provide a semiconductor integrated circuit device that can minimize the increase in hardware size and transfer data between an EEPROM and a RAM without placing a burden on software. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, a direct coupling path is provided for coupling the data line of the EEPROM and the data line of the RAM, and a means for controlling the direct transfer of data between the EEPROM and the RAM by the direct coupling path is provided. 6 [Operation] According to the above-described means, when it is necessary to transfer data between the EEPROM and the RAM, the direct connection path and the control means perform direct data transfer, thereby achieving sequential control by the CPU. (EEPR)
By directly transferring data between the OM and the RAM, the above objective of enabling direct data transfer without placing a burden on software can be achieved.

[Embodiment] FIG. 6 shows an example of a single-chip microcomputer with a built-in EEPROM to which the present invention is applied.

In the figure, although not particularly limited, each circuit block surrounded by a two-dot chain line A is formed on one semiconductor chip such as a single crystal silicon substrate.

In the figure, 1 is an EEPROM used for semi-permanent storage of data as a data file or the like.

A RAM 2 is mainly used for temporary storage of data or as a work area for the CPU. 3 is a CPU (central processing unit) having data processing functions, such as an accumulator, a status register, a stack pointer, and a program counter.

It is composed of a CPU controller, an arithmetic and logic unit, etc. In addition, 4 is a ROM (Read) in which software programs for various data processing are stored.
0nly Memory), and is constituted by a mask type ROM, although there is no particular limitation. 5 is a peripheral circuit, for example.

Includes timer, serial communication interface, etc. Reference numeral 6 denotes an input/output circuit for exchanging addresses, data, and control signals with the outside of the semiconductor integrated circuit. The above circuit blocks are interconnected with the CPU 3 at the center by a bus 7 consisting of an address bus, a data bus, and the like. Note that illustration of control signals for each memory and peripheral circuit is omitted.

Here, in particular, EEFROMI is a non-volatile storage device that is electrically writable and erasable, such as a bank I/O.
It is used for semi-permanent storage of data such as deposit and withdrawal information on the C card.

FIG. 1 shows an example of a specific configuration of the EEPROM 1 and RAM 2 (7).

In FIG. 1, 11 is an EEPROM storage element matrix (hereinafter referred to as EEPROM7L/A), and 12 is an EEPROM storage element matrix.
M address decoder, 13 is column C) latch circuit,
14 is a write control circuit having a sequence control function of the operation of the EEPROM array 11 during the writing period of the EEPROM array 11, 21 is a RAM storage element matrix (hereinafter referred to as a RAM array), and 22 is a RAM address decoder. be. EEPROM1 and RAM2 are each independently connected to an address bus and a data bus. A conventional semiconductor integrated circuit is provided with the above circuit blocks.

Writing to the RAM is performed by supplying an address and data via an address bus and a data bus, respectively, as well as a write signal (not shown). Further, reading is performed by supplying an address via an address bus and a read signal (not shown), and data is output onto a data bus.

On the other hand, reading from the EEPROM is performed by applying address and read signals in the same manner as described above. Writing is performed by giving an address, data, and a write signal. At this time, although there is no particular restriction, consecutively input data within the same row address is held in the column switch 13. Then, the data can be written all at once. Furthermore, due to the long write time of EEPROM, the EEPROM is isolated from other circuit blocks during the write period and the write address and data are retained during said period. What is the operation during the above period?

This is performed under the control of the write control circuit 14. The write control circuit 14 has a sequence control function necessary for the control.

Furthermore, in FIG. 1, address registers 81 and 82 are writable by software and hold row address information of EEPROMI and RAM2, respectively. 83 is activated by software, and the address registers 81 and 82 and the switch 84 are activated by software.
85 is a transfer control circuit for controlling the operation of E
This is a direct coupling path that connects the EPROM array 11 and the RAM array 21. Note that other circuit blocks and control lines are omitted in FIG. Although not particularly limited, the EEPROM array 11 and the RAM array 21
The column addresses are shared, and the data lines of the EEPROM array 11 and the data lines of the RAM array 21 are all connected by a direct coupling path 85 via the switch 84. The transfer control circuit 83 has flags MOVl and MOv2 (not shown), and these flags MOv1
, MOV2 can be set using software and reset using hardware.

First, simultaneous data transfer from EEPROMI to RAM2 will be explained.

First, address register 81 and address register 82
by writing to the EEPROM array 11,
While specifying the row address of the RAM array 21,
Flag MOv1 in the transfer control circuit 83 is set. This sets the simultaneous transfer mode from EEPROMI to RAM2.

The contents of the address registers 81 and 82 are input to the address decoders 12 and 22, respectively, by a control signal from the transfer control circuit 83, and the EEPR is
A selection signal is supplied to the OM array 11 and the RAM array 21. Further, the switch 84 is turned on by a control signal from the transfer control circuit 83, and the EEPR
A read signal is supplied to the OM array 11, a write signal is supplied to the RAM array 21, and the EEPROM array 1
Simultaneous transfer from the specified row address of 1 to the specified row address of RAM array 21 is performed. Thereafter, although there is no particular restriction, the flag MOVI is reset by hardware after the simultaneous transfer ends.

On the other hand, to simultaneously transfer data from the RAM 2 to the EEPROMI, write to the address registers 81 and 82 in the same manner as described above to specify the row addresses of the EEPROM array 11 and RAM array 21, respectively, and set the flag in the transfer control circuit 83. Set MOV2. This sets the simultaneous transfer mode from RAM2 to EEPROMI. In response to a control signal from the transfer control circuit 83, the contents of the address registers 81 and 82 are first input to the address decoders 12 and 22, respectively, and the switch 84 is turned on. A read signal is supplied to the array 21. Along with this, the contents of the specified row address of the RAM array 21, that is, page data, are transferred to the column latch circuit 13, and then the write control circuit 1
4, the contents of the column latch circuits 13 are simultaneously written into the EEPROM array 11 all at once. After the transfer to the column latch circuit 13 is completed, the flag MOV2 is reset by hardware.

It will be done.

Although not particularly limited, EEPROM array 11
During the writing period of , operation of flags MOVI and MOV2 is prohibited. Also, the flag MOVI
While one of MOV2 and MOV2 is set, operation of the other is prohibited, and.

Access to the EEPROM array 11 and RAM array 21 for reading is prohibited.

FIG. 2 shows a specific example of the circuit configuration of the transfer control circuit 83 in the above embodiment.

In FIG. 2, 71 is an address bus.

711.712 are EEPROMi! obtained by decoding the address information on the address bus 71. l selection signal and R
This is an AM selection signal.

The transfer control circuit 83 is shown as an area surrounded by a dashed line B, and is connected to the storage device 831 . A storage device 832 having a flag MOV2, an exclusive OR gate G1, and a plurality of control gate groups GGI, GG2.
Consisting of The switch 84 is an N-channel MO8 (
Me t a 10xida Sem1conduc
tor) It is made up of transistors and is controlled to be turned on and off by a control signal supplied via a control line 93.

First, consider the case where both flags MOVI and MOV2 are reset (10 flags). In this case, low-level signals are supplied to the two input terminals of gate G1, and the output (control line 93) is set to low level.This turns off the switch 84.In this state, the EEPROMI and RA
M2 is an address and read signal 73 .M2 supplied from the address bus 71 . Each circuit operates independently according to a write signal 74, and inputs and outputs data to and from other circuit blocks via a data bus 72.

On the other hand, if either flag MOVI or flag MOV2 is set (high), gate G1
In other words, the control line 93 becomes high level, and the control gate groups GGI, GO2 control EEPROMI, RA.
M24: Supply of the address signal 71 to the target is prohibited 6
Instead, the contents of address registers 81 and 82 are applied to EEPROM1 and RAM2, respectively, to designate a row address, and switch 84 is turned on. At this time, if the flag MOVI is set, reading and writing are instructed to EEPROMI and RAM2, respectively, and EEPROMI
from the specified low address.

Simultaneous transfer to the designated row address of RAM2 is performed. On the other hand, if flag MOV2 is set, EEP
Writing and reading are instructed to ROM1 and RAM2, respectively. Then, the switch 84 is turned on, and data is transferred from the specified row address of the RAM 2 to the column latch circuit 13 and latched.
The contents of are written to the specified load address of EEPROMI.

As described above, it is possible to simultaneously transfer a plurality of data between arbitrary row addresses of each of EEPROMI and RAM2. Furthermore, independent data read and write operations of EEPROMI and RAM2 are enabled.

According to the above-mentioned means, a direct coupling path is provided for coupling the data line of the EEPROM and the data line of the RAM, and the direct coupling path is enabled to connect the EEPROM to the data line of the RAM.
Setting a simultaneous transfer mode that enables simultaneous data transfer between the ROM and RAM or an independent operation mode that disables the direct coupling path and allows the EEPROM and RAM to operate independently of each other. Since we have provided possible control means.

Simultaneous data transfer between EEPROM and RAM is CP
Because it can be performed without using control signals from U, the burden on the software is minimized and the EEPRO
The effect is that data can be transferred simultaneously between M and RAM.

Further, according to the above-described means, a direct coupling path is provided for coupling the data line of the EEPROM and the data line of the RAM, and the direct coupling path is enabled, so that the E E
A simultaneous transfer mode that enables simultaneous data transfer between the P ROM and RAM or an independent operation mode that disables the direct coupling path and allows the EEPROM and RAM to operate independently of each other can be set. Since the control means is provided, not only the simultaneous transfer mode but also the independent operation mode can be set.
Of course, it is possible to simultaneously transfer data between
PROM and RAM can read and write data independently of each other.
The effect of being able to write is obtained.

FIG. 3 shows a block diagram of a second embodiment of the present invention.

The block configuration of the second embodiment is substantially the same as that of the first embodiment shown in FIG. However, in this embodiment, the capacity of EEPROMI is divided according to the capacity of RAM2. for example.

The column address is 32. In other words, if one page is 32 bytes, and RAM2 is 128 bytes (32 bytes x 4 lines) and EEPROMI is 2 bytes (32 bytes x 64 lines, where = 1024), E E
F ROM 1 is divided into 16 sections of 4 lines each. below,
In EEPROMI, this divided unit is called a bank.

In this embodiment, the row address in each bank of the EEPROMI is shared by the row address selection signal of the RAM2. Furthermore, EEPROM address register 8
1 can be written to by software as in the first embodiment, and by writing, the EEPROM array 1
It is possible to specify any one bank.

In this way, any one row of RAM array 21 always corresponds to one row in EEPROM1.

The transfer control circuit 83 also has a flag MOV3 that can be set/reset by software.
When V3 is set, the switch 84 is turned on, and when it is reset, the switch 84 is turned off.

First, consider the case where flag MOV3 is set and switch 84 is turned on. In this state, EE
Direct connection path 85 between PROM array 11 and RAM array 21 is enabled, and direct input of data to the bank selected by address register 81 via data bus 72 is prohibited. When reading any address within the selected bank,
The contents of the specified address (1 byte) are transferred to data bus 7.
At the same time, the contents (page data) of the row address including the specified address are simultaneously transferred to the corresponding row address in the RAM array 21 via the direct connection path 85. On the other hand, when writing to an arbitrary address within the selected bank, first the RAM array 2 corresponding to the row address including the specified address is
The contents of the row address within 1 are transferred to the column switch circuit 13 via the direct coupling path 85 and latched, and then the contents of the column switch circuit 13 are simultaneously transferred to the EEPR.
Written to OMII.

On the other hand, if flag MOV3 is in the reset state,
Switch 84 is turned off and EEPROMI and R
AM2 operates independently. Also, EEPRO
Unselected banks of MI operate independently of RAM2.

FIG. 4 shows a block diagram of the transfer control circuit 83 in the second embodiment.

In the figure, 833 is a storage device having a flag MOV3, and 834 is a comparator.

Comparator 834 compares the contents of address register 81 with the address on address bus 71 to determine whether the specified address exists within the selected bank.

The comparison may be performed for the number of bits required for determination. For example, if the column address is 32 bytes and each bank has 4 rows, these 7 bits are ignored. The output of comparator 834 is:

It is set to a high level only when the comparison results match, that is, when the designated address exists in the bank selected by the address register 81.

In FIG. 4, when the flag MOV3 is set and reading in the designated bank is performed, control [93
and read signal 73 are both set to high level. As a result, EEFROMI is instructed to read the specified row address, and RAM2 is instructed to read the specified row address.
A row address whose selection signal is shared with the designated row address in ROM1 is selected, and writing is instructed via logic gate G2, causing simultaneous transfer from the designated row address in EEPROMI to the corresponding row address in RAM2. It is done.

On the other hand, when writing in the designated bank is performed, writing is instructed to EEPROMI in the same manner as described above, the corresponding row address is selected to RAM2, and the comparator 834 The output instructs reading via the opened logic gate G3, and
The switch 84 is turned on, and data is simultaneously transferred from the corresponding row address of the RAM 2 to the designated row address of the EEPROMI. Although not particularly limited, direct input of data to the EEPROMI on the data bus 72 is prohibited at this time.

In addition, in FIG. 4, EEPROM 1 and RA
The address input line to M2 is omitted.

As described above, in this embodiment, it is possible to simultaneously transfer a plurality of data between EEFROM1 and RAM2, and it is also possible to read and write data independently from EEPROM1 and RAM2 (7).
By dividing OMI and sharing the row address selection signal with RAM2, a simpler ellipse can be achieved.
The hardware scale can be reduced.

This embodiment is particularly effective when the block size of data handled on the present semiconductor integrated circuit is equal to the RAM capacity. In addition, RAM2 is larger than the block size.
If the capacity of is large.

The capacity of EEPROMI may be divided according to the block size. In this case, RAM2.

Only the portion corresponding to the block size is EEFRO
It is sufficient if it corresponds to MI.

FIG. 5 shows a block diagram of a third embodiment of the present invention.

In this embodiment, the area on the RAMZ where a plurality of data can be transferred simultaneously to and from the EEPROM1 is limited to the first row 211.

As in the second embodiment, the transfer control circuit 83 sets the flag M
OV3 and when flag MOV3 is set, if an arbitrary address of the EEPROM array 11 is read, the contents of the specified address (1 byte) will be read.
is output onto the data bus 72, and the contents (page data) of the row address including the specified address are simultaneously transferred to the first row of the RAM array 21 via the direct connection path 85. ing. On the other hand, E
When writing to an arbitrary address in the EPROM array 11, the contents of the first row 211 in the RAM array 21 are first sent to the column latch circuit 13 via the direct coupling path 85 and latched. The contents of the latch circuit 13 are written to the EEPR○M array 11. Although there is no particular restriction, in this case, data bus 7
Direct input of data on EEPROM array 11 to EEPROM array 11 is prohibited.

On the other hand, if flag MOV3 is in the reset state,
Similar to the second embodiment, the EEPROM array 11
and RAM array 21 are operated independently.

Although not particularly limited, RAM array 2].

The first row 211 and other regions may be formed separately.

This embodiment is particularly effective when it is not necessary to simultaneously process data stored over a plurality of pages on the EEPROM array 11, that is, when it is sufficient to process data page by page.

In addition, in the third embodiment, it is possible to transfer only a part of the RAM, so the hardware is simple and the occupied area is small.
Although the invention made by the inventor has been specifically explained based on examples, the invention is not limited to the above-mentioned examples. It goes without saying that various changes can be made without departing from the spirit of the invention. For example, direct coupling paths do not need to be provided for all data lines, and direct coupling paths may be provided for only some data lines. Or, E
A configuration may also be adopted in which one data line of the EPROM corresponds to a plurality of data lines of the RAM and can be switched by a switch. Further, the column addresses of the EEPROM and RAM may be different. Further, the specific circuit of each circuit block may be any circuit as long as it performs the same operation as described above.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to a single-chip microcomputer, which is the field of application that formed the background of the invention.
The present invention is not limited thereto, and can be used for general semiconductor integrated circuits incorporating nonvolatile memory.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, a direct coupling path is provided for coupling the EEPROM and RAM, and the EEPROM is connected to the EEPROM by the direct coupling route.
By providing a means for controlling direct data transfer between the ROM and RAM, direct data transfer between the EEPROM and RAM can be performed without intervening sequential control by the CPU.

The burden on software can be reduced and the increase in hardware scale can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a specific configuration example of an EEPROM and RAM according to a first embodiment of the present invention, FIG. 2 is a specific circuit diagram of a transfer control circuit of the first embodiment, and FIG. is a block diagram showing the second embodiment of the present invention, FIG. 4 is a specific circuit diagram of the transfer control circuit of the second embodiment, FIG. 5 is a block diagram showing the third embodiment, and FIG. 1 is a block diagram showing an example of a single-chip microcomputer equipped with an EEPROM to which the present invention is applied. 1... EEPROM, 11... EEPROM storage element matrix, 12... EEPROM address decoder, 13... Column latch circuit, 14...
・Write control circuit, 2...RAM, 21...R
AM storage element matrix, 22...RAM address decoder, 3...CPU, 4...ROM, 5...
Peripheral circuit, 6... Input/output circuit, 71... Address bus, 72... Data bus, 73... Read signal, 74... Write signal, 81.82...・Address register, 83...Transfer control circuit, 831~
833...Storage device, 834...Comparator, 84
...Switch, 85...Direct coupling path. 1\, Agent: Patent Attorney Katsuma Ogawa - P11. +・Ya, - Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. d

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device having a non-volatile memory device and a volatile memory device each having independent data input/output paths, wherein the non-volatile memory device and the volatile memory device are connected directly to each other. A semiconductor integrated circuit device, further comprising a coupling path, to enable direct transfer of a plurality of data between the nonvolatile memory device and the volatile memory device. 2. The semiconductor integrated circuit device according to claim 1, further comprising means for setting whether direct data transfer is enabled or not. 3. The semiconductor integrated circuit device according to claim 1 or 2, further comprising means for setting the transfer direction of the direct data transfer. 4. The path that directly connects the nonvolatile storage device and the volatile storage device is a combination of part or all of the data line of the nonvolatile storage device and the data line of the volatile storage device. A semiconductor integrated circuit device according to claims 1 to 3. 5. The semiconductor integrated circuit device according to claims 1 to 4, wherein row addresses of the nonvolatile memory device and the volatile memory device can be selected by the same selection signal. .