JPS63180875A - Radar signal processor - Google Patents

Radar signal processor

Info

Publication number
JPS63180875A
JPS63180875A JP62013579A JP1357987A JPS63180875A JP S63180875 A JPS63180875 A JP S63180875A JP 62013579 A JP62013579 A JP 62013579A JP 1357987 A JP1357987 A JP 1357987A JP S63180875 A JPS63180875 A JP S63180875A
Authority
JP
Japan
Prior art keywords
threshold
small
memory
area
target
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62013579A
Other languages
Japanese (ja)
Inventor
Masami Mochii
餅井 雅美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62013579A priority Critical patent/JPS63180875A/en
Publication of JPS63180875A publication Critical patent/JPS63180875A/en
Pending legal-status Critical Current

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  • Radar Systems Or Details Thereof (AREA)

Abstract

PURPOSE:To achieve a suppression of the rate of erroneous target detection and an upgrading of the rate of target detection in an area where clutters exist, by subdividing the unit of a threshold control region in an area relatively difficult in the detection of a target. CONSTITUTION:When a small area is subdivided into more than one part and when there is a large threshold difference between subdivided regions, the difference is detected with a small region division/expansion judging circuit 2 and a representative threshold in a small region is stored with a memory control circuit 5 into a threshold memory 3 and threshold in the remaining region of the small area is stored temporarily into an auxiliary memory 4. When radar signal level is uniform among continuous small areas, the continuous small areas are determined with the circuit 2 to be the same in threshold. The memory 3 records the threshold thus determined for use in the subsequent radar rotation cycle together with an indicator identifying the threshold as such in a subdivided region or in continuous same areas. The auxiliary memory 4 records the subdivided regions provisionally. Thus, the rate of target detection can be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、レーダ信号処理装置の目標検出装置に関し、
特にレーダ覆域を小領域に分割し、小領域単位でしきい
域制御することにより目標を検出する目標検出装置に関
する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a target detection device for a radar signal processing device.
In particular, the present invention relates to a target detection device that detects a target by dividing a radar coverage area into small areas and performing threshold control in units of small areas.

〔従来の技術〕[Conventional technology]

従来、この種の目標検出のためのレーダ信号処理では、
処理単位である小領域の大きさは、レーダ覆域の全域に
わたり、距離方向及び方位方向に同一単位で分割され、
この小領域単位でのしきい値制御のためのしきい値記憶
回路をレーダ覆域全域に対して保有し、制御のための単
位は、変らずに一定となっていた。
Conventionally, in radar signal processing for this type of target detection,
The size of the small area, which is a processing unit, is divided into the same unit in the distance direction and azimuth direction over the entire radar coverage area,
A threshold storage circuit for threshold control in units of small areas is provided for the entire radar coverage area, and the units for control remain constant.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のレーダ信号処理装置の目標検出装置は、
目標検出のためのしきい値は、小領域内では、同一値で
あるため、小領域内に目標としての航空機と、その他の
対象、たとえばグランド・クラッタ・ウェザ・クラッタ
・チャフ等が同時に存在する場合、それぞれからのレー
ダ反射信号の振幅の大きさによっては、目標を極力検出
するためのしきい値制御を行なうとその他のクラッタ等
も、誤目標として検出され必要な誤目標警報率が得られ
ずまた一方、誤目標の検出を極力抑圧するためのしきい
値制御を行なうと、目標の検出ができなくなり目標検出
率が劣化するという欠点がある。この欠点をおぎなうた
めに小域領域の単位を小さくする方法もあるが、これに
よれば、しきい値を記憶させるための記憶回路が比例し
て大規模となる欠点がある。
The target detection device of the conventional radar signal processing device described above is
Since the threshold for target detection is the same value within a small area, an aircraft as a target and other objects such as ground clutter, weather clutter, chaff, etc. exist simultaneously within the small area. In this case, depending on the amplitude of the radar reflection signal from each, if threshold control is performed to detect the target as much as possible, other clutter will also be detected as false targets and the necessary false target alarm rate may not be obtained. On the other hand, if threshold control is performed to suppress the detection of erroneous targets as much as possible, there is a drawback that the target cannot be detected and the target detection rate deteriorates. In order to overcome this drawback, there is a method of reducing the unit of the small area, but this method has the drawback that the storage circuit for storing the threshold value becomes proportionally large in scale.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のレーダ信号処理装置は、目標検出のためのしき
い値の判定において、基本処理単位である小領域に対し
、その小領域を更に細分割化し、小領域内でレーダ信号
レベルが均一でない場合にはこの細分割領域の単位でし
きい値を判定する回路と、連続する小領域間でレーダ信
号レベルが均一である場合は、この連続する小領域を同
一しきい値として判定する回路と、判定されたしきい値
を次のレーダ回転周期において使用するために記録し、
しきい値の他に細分割領域のしきい値か、連続同一領域
のしきい値かを示す指標を併せて記録する記憶メモリー
と細分割領域を暫定的に記録する補助メモリを有してい
る。
In determining the threshold value for target detection, the radar signal processing device of the present invention further subdivides the small area, which is the basic processing unit, so that the radar signal level is not uniform within the small area. In this case, there is a circuit that determines the threshold value in units of this subdivided region, and a circuit that determines the threshold value for these consecutive small regions as the same threshold when the radar signal level is uniform between consecutive small regions. , recording the determined threshold for use in the next radar rotation cycle;
In addition to the threshold value, it has a storage memory that also records an index indicating whether it is a threshold value for a subdivision area or a threshold value for the same continuous area, and an auxiliary memory that temporarily records the subdivision area. .

〔実施例〕 次に本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

しきい値判定回路l及び小領域分割/拡大判定回路2r
i、しきい値を検出し、決定するだめの回路でありしき
い値記憶メモリー3.補助メモリ4及びメモリー制御5
ri、しきい値を次のレーダ回転周期まで保持するだめ
の回路であり、振幅比較回路6は、レーダ信号6としき
い値7とを比較し目標の有無を判定する回路である。入
力されるレーダ信号7の振幅値とレーダ目標信号9から
、しきい値判定回路1は、次のレーダ回転周期のしきい
値の値を小領域単位に判定し決定する。通常は小領域単
位で決定されたしきい値がしきい値記憶メモリー3に記
憶され次の回転周期に使用されるがしきい値判定回路で
は、小領域内を更に2以上に細分割してその細分割領域
間でしきい値の差が大きい場合小領域分割/拡大判定回
路2がそれを検知し、メモリー制御回路5で、当該小領
域の代表的しきい値は従来のしきい値記憶メモリ3に記
録し、当該小領域の残りの領域におけるしきい値は補助
メモリ4に一度記録する。その後、同一方位の小領域に
おいて、しきい値判定回路1にて決定したしきい値が、
当該小領域だけでなく、相隣子2つの小領域において同
一しきい値であることか小領域分割/拡大判定回路2で
判定されるとこれによりメモリー制御回路5は後続する
2つめの小領域のしきφ値はしきい値記憶メモIJ −
3K記録せず、同一しきい値であったことの指標のみを
、同一しきい値となった当該2連続小領域の先行する小
領域のしきい値に付加し、しきい値記憶メモリー3に記
録し、本来、後続する小領域のしきい値が記録されるべ
きしきい値記憶メモリー3の番地は空きとなる。この空
きは、次の小領域に対するしきい値判定結果により埋め
られることにより小領域連続同一しきい値が判定された
回数だけ、同一方向の小領域においてしきい値記憶メモ
リー3に空きができる。同一方向の全小領域に対するし
きい値判定が終るとメモリ制御回路5II′iシきい値
記憶メモリー3の空きの数だけ、先に小領域内で細分割
のしきい値が記録されている補助メモリー4からしきい
値データを読み出し、この細分割された当該小領域の代
表しきい値の記録されているしきい値記憶メモリー3の
番地に続く番地に挿入記録され、これに続く小領域のし
きい値データはしきい値記憶メモリー3の中で1番地シ
フトされる。同一方向の小領域において小領域連続同一
しきい値となる数と小領域細分割によりしきい値が異な
るために記録されている補助メモリー4のしきい値の数
において、前者が多い場合は全ての細分割しきい値が少
ない場合は、一度細分割されて補助メモリー4に記録さ
れたしきい値も、しきい値記憶メモリー3に空きがない
ため、最初に記録された代表しきい値のみが使用され、
結果として細分割されず、通常の小領域として扱われる
Threshold determination circuit l and small area division/enlargement determination circuit 2r
i. Threshold memory, which is a circuit for detecting and determining the threshold; 3. Auxiliary memory 4 and memory control 5
The amplitude comparison circuit 6 is a circuit that compares the radar signal 6 and the threshold value 7 to determine the presence or absence of a target. Based on the amplitude value of the input radar signal 7 and the radar target signal 9, the threshold value determination circuit 1 determines and determines the value of the threshold value for the next radar rotation period in units of small areas. Normally, the threshold determined for each small area is stored in the threshold storage memory 3 and used for the next rotation cycle, but in the threshold judgment circuit, the small area is further subdivided into two or more. If the difference in threshold values between the sub-division areas is large, the small-area division/enlargement determination circuit 2 detects this, and the memory control circuit 5 stores the typical threshold value of the sub-area in the conventional threshold value memory. The threshold values for the remaining areas of the small area are recorded once in the auxiliary memory 4. After that, in the small area in the same direction, the threshold determined by the threshold determination circuit 1 is
When the small area division/enlargement determination circuit 2 determines whether the threshold value is the same not only for the particular small area but also for two neighboring small areas, the memory control circuit 5 determines whether the threshold value is the same for the two neighboring small areas. The threshold φ value is the threshold value memory memo IJ −
3K is not recorded, and only the index indicating that the threshold value was the same is added to the threshold value of the small area preceding the two consecutive small areas that have the same threshold value, and is stored in the threshold storage memory 3. The address of the threshold storage memory 3 where the threshold value of the subsequent small area should originally be recorded becomes empty. This empty space is filled with the threshold value determination result for the next small area, thereby creating an empty space in the threshold storage memory 3 in the small area in the same direction for the number of times that the same threshold value has been determined consecutively for the small area. When the threshold judgment for all small areas in the same direction is completed, the memory control circuit 5II'i stores the sub-division thresholds in the small areas as many times as there is free space in the threshold storage memory 3. Threshold data is read from the memory 4, inserted and recorded at the address following the address of the threshold storage memory 3 where the representative threshold value of the subdivided small area is recorded, and the data of the subsequent small area is recorded. The threshold data is shifted by one address in the threshold storage memory 3. The number of consecutive small areas with the same threshold in the same direction and the number of threshold values in the auxiliary memory 4 recorded because the thresholds differ due to subdivision of the small area, if the former is large, all If there are few subdivision thresholds, the thresholds that have been subdivided and recorded in the auxiliary memory 4 will only be the first recorded representative threshold because there is no space in the threshold storage memory 3. is used,
As a result, it is not subdivided and is treated as a normal small area.

第2図は以上の動作の概念図である。Ari小領域の分
割の例として距離と方位により区切られた同一方向の小
領域#1〜#10を示し、Briこれらの小領域に対す
るしきい値の一例を示すもので小領域の#2と#8が細
分割しきい値を有し、小領域の#4と#6が連続同一し
きい値を持つ小領域であるとを示している。Cはしきい
値記憶メモリー3の記憶内容を示すものでT Hz a
 THs a d小領域#2.#8の代表しきい値が記
録されていることを示し、■は細分割小領域であること
をeは連続同一しきい値小領域であることを示す。I)
ri補助メモリー4の内容でTHxb 、 T Hsb
ri小領域#2、#8の細分割領域の残りの領域に対す
るしきい値の記憶されていることを示す。C′は最終的
なしきい値記憶メモリー3の記録内容を示し、“補助メ
モリー4のTHzb 、 THsbが当該小領域の代表
しきい値T H2m 、 T H2b後に捜入されてい
ることを示している。
FIG. 2 is a conceptual diagram of the above operation. Ari shows small areas #1 to #10 in the same direction separated by distance and direction as an example of dividing a small area, and Bri shows an example of a threshold value for these small areas. 8 has a subdivision threshold, and small regions #4 and #6 are small regions having the same continuous threshold. C indicates the memory contents of the threshold value storage memory 3, and T Hz a
THs a d small area #2. Indicates that the representative threshold value of #8 is recorded, ■ indicates a subdivision small area, and e indicates a continuous same threshold small area. I)
THxb, T Hsb with the contents of ri auxiliary memory 4
This indicates that the threshold values for the remaining areas of the subdivision areas of ri small areas #2 and #8 are stored. C' indicates the final recorded contents of the threshold value storage memory 3, and indicates that "THzb and THsb of the auxiliary memory 4 are searched after the representative threshold values T H2m and T H2b of the relevant small area." .

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、レーダ信号がクラッタ等
の反射がない領域ではレベルか比較的均一であるのでし
きい値制御の領域の単位を拡大し、クラッタ等による誤
目標となる要因が多く、目標の検出が相対的に難かしい
領域においてはしきい値制御の領域の単位を細分化する
ことにより、従来の装置よりもしきい値記憶のためのメ
モリーの容量を大幅に増やすことなく、レーダ信号の状
況に合った目標検出のためのしきい値制御を可能とし、
クラッタのある領域での誤目標検出率の抑圧と目標検出
率を改善できる効果がある。
As explained above, in the present invention, the level of the radar signal is relatively uniform in an area where there is no reflection from clutter, etc., so the unit of the area for threshold control is expanded, and there are many causes of erroneous targets due to clutter etc. In areas where target detection is relatively difficult, by subdividing the unit of threshold control area, the radar can be Enables threshold control for target detection that matches signal conditions,
This has the effect of suppressing the false target detection rate in areas with clutter and improving the target detection rate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のレーダ信号処理装置のブロック図、第
2図は、第1図の動作内容を示す概念図である。 1・・・・・・しきい値判定回路、2・・・・・・小領
域分割/拡大判定回路、3・・・・・・しきい値記憶メ
モリー、4・・・・・・補助メモリー、5・・・・・・
メモリ制御回路、6・・・・・・振幅比較回路、7・・
・・・・レーダ信号、8・・・・・・しきい値、9・・
・・・・レーダ目標信号、A・・・・・・小領域の分割
の例、B・・・・・・判定されたしきい値の例、C・・
・・・・しきい値記憶メそり一の内容。
FIG. 1 is a block diagram of a radar signal processing device of the present invention, and FIG. 2 is a conceptual diagram showing the operation contents of FIG. 1. 1...Threshold judgment circuit, 2...Small area division/enlargement judgment circuit, 3...Threshold memory memory, 4...Auxiliary memory , 5...
Memory control circuit, 6... Amplitude comparison circuit, 7...
...Radar signal, 8...Threshold value, 9...
...Radar target signal, A...Example of small area division, B...Example of determined threshold value, C...
...Contents of threshold memory memorization.

Claims (1)

【特許請求の範囲】[Claims] レーダ目標検出装置の航空機等の目標検出制御方式にお
いて、レーダ覆域を複数の2次元的又は3次元的な小領
域に分割し、これらの小領域を目標出念の処理単位とし
、目標からの反射信号の振幅値に対し、小領域単位で目
標検出のためのしきい値制御を行ない、このしきい値わ
超える目標信号の振幅値を目標と判定する機能を含むこ
とを特徴とするレーダ信号処理装置。
In the target detection control method of radar target detection equipment for aircraft, etc., the radar coverage area is divided into a plurality of two-dimensional or three-dimensional small areas, and these small areas are used as processing units for target estimating, and the detection from the target is A radar signal characterized by including a function of performing threshold control for target detection on an amplitude value of a reflected signal in small area units and determining that an amplitude value of a target signal exceeding this threshold value is a target. Processing equipment.
JP62013579A 1987-01-22 1987-01-22 Radar signal processor Pending JPS63180875A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62013579A JPS63180875A (en) 1987-01-22 1987-01-22 Radar signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62013579A JPS63180875A (en) 1987-01-22 1987-01-22 Radar signal processor

Publications (1)

Publication Number Publication Date
JPS63180875A true JPS63180875A (en) 1988-07-25

Family

ID=11837079

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62013579A Pending JPS63180875A (en) 1987-01-22 1987-01-22 Radar signal processor

Country Status (1)

Country Link
JP (1) JPS63180875A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023084627A1 (en) * 2021-11-10 2023-05-19 株式会社Fuji Measuring device and robot system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827074A (en) * 1981-08-12 1983-02-17 Nec Corp Apparatus for trapping moving object
JPS6026187A (en) * 1983-07-22 1985-02-09 Jidosha Kiki Co Ltd Pump system
JPS629186B2 (en) * 1982-03-05 1987-02-26 Sumitomo Metal Ind

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827074A (en) * 1981-08-12 1983-02-17 Nec Corp Apparatus for trapping moving object
JPS629186B2 (en) * 1982-03-05 1987-02-26 Sumitomo Metal Ind
JPS6026187A (en) * 1983-07-22 1985-02-09 Jidosha Kiki Co Ltd Pump system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023084627A1 (en) * 2021-11-10 2023-05-19 株式会社Fuji Measuring device and robot system

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