JPS63179777U - - Google Patents

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Publication number
JPS63179777U
JPS63179777U JP7121087U JP7121087U JPS63179777U JP S63179777 U JPS63179777 U JP S63179777U JP 7121087 U JP7121087 U JP 7121087U JP 7121087 U JP7121087 U JP 7121087U JP S63179777 U JPS63179777 U JP S63179777U
Authority
JP
Japan
Prior art keywords
pulse width
pulse
switching transistor
capacitor
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7121087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7121087U priority Critical patent/JPS63179777U/ja
Publication of JPS63179777U publication Critical patent/JPS63179777U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のブロツク構成図。
第2図は上記実施例の各部の動作波形図。第3図
は従来例のブロツク構成図。 1,8……入力端子、2,3……第二および第
一のスイツチングトランジスタ、4……ダイオー
ド、5……チヨークコイル、5a,5b……チヨ
ークコイルの端部、6……コンデンサ、7,9…
…出力端子、10……パルス発生器、11……パ
ルス幅制御回路、12……直流電源、13……ツ
エナーダイオード、14……抵抗器、15……コ
ンデンサ、16……サイリスタ、17……ヒユー
ズ。
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is an operation waveform diagram of each part of the above embodiment. FIG. 3 is a block diagram of a conventional example. 1, 8... Input terminal, 2, 3... Second and first switching transistors, 4... Diode, 5... Chiyoke coil, 5a, 5b... End of chiyoke coil, 6... Capacitor, 7, 9...
... Output terminal, 10 ... Pulse generator, 11 ... Pulse width control circuit, 12 ... DC power supply, 13 ... Zener diode, 14 ... Resistor, 15 ... Capacitor, 16 ... Thyristor, 17 ... Hughes.

Claims (1)

【実用新案登録請求の範囲】 第一のスイツチングトランジスタ3と、 このスイツチングトランジスタの間けつ作動出
力によりチヨークコイル5を介して充電されるコ
ンデンサ6と、 このコンデンサの充電電圧を検出し上記スイツ
チングトランジスタのベースに供給する出力パル
スのパルス幅を上記充電電圧が安定するように制
御するパルス幅制御回路11と、 を備えた直流・直流コンバータにおいて、 上記第一のスイツチングトランジスタに直列に
接続された第二のスイツチングトランジスタ2と
、 この第二のスイツチングトランジスタのベース
に上記パルス幅制御回路と同期しこのパルス幅制
御回路の出力より長いパルス幅のパルスを送出す
るパルス発生器10と、 を備えたことを特徴とする直流・直流コンンバ
ータ。
[Claims for Utility Model Registration] A first switching transistor 3, a capacitor 6 which is charged via a switch coil 5 by the intermittent operation output of this switching transistor, and a capacitor 6 that detects the charging voltage of this capacitor and performs the above-mentioned switching. a pulse width control circuit 11 that controls the pulse width of the output pulse supplied to the base of the transistor so that the charging voltage is stabilized; a second switching transistor 2; a pulse generator 10 which synchronizes with the pulse width control circuit and sends a pulse having a pulse width longer than the output of the pulse width control circuit to the base of the second switching transistor; A DC/DC converter characterized by being equipped with.
JP7121087U 1987-05-13 1987-05-13 Pending JPS63179777U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7121087U JPS63179777U (en) 1987-05-13 1987-05-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7121087U JPS63179777U (en) 1987-05-13 1987-05-13

Publications (1)

Publication Number Publication Date
JPS63179777U true JPS63179777U (en) 1988-11-21

Family

ID=30913559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7121087U Pending JPS63179777U (en) 1987-05-13 1987-05-13

Country Status (1)

Country Link
JP (1) JPS63179777U (en)

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