JPS63173206A - Integral detecting circuit - Google Patents

Abstract

PURPOSE:To constitute the titled circuit so that is is scarcely influenced b6y a variation of a power source, and strong against the same phase noise, and to make it unnecessary to provide a bypass capacitor of a large capacity, by adopting a circuit constitution of a differential type. CONSTITUTION:Input signals supplied to the first and the second transistors 11, 12 through input terminals 1, 2 are differentiated by a capacitor 3 for differentiating a current, and become collector output currents of each transistor 11, 12. Simultaneously, in each emitter of both the transistors 11, 12 voltages of the input signals are obtained as they are, each input signal voltage is integrated by an integrating circuit 4, and thereafter, supplied to a differential amplifier consisting of transistors 14, 13 through the respective buffers of transistors 16, 15 and an output is added to each collector current of the second and the first transistors 12, 11. In such a way, a current which has synthesized a differential current, and an inverted current flows through each load resistance 17, 18 of the transistors 11, 12, by which output voltage are fetched from each output terminal 7, 8, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to an integral detection circuit for detecting data by reproducing signals recorded on a recording medium such as a magnetic disk.

B0 Summary of the Invention The present invention provides an integral detection circuit for detecting a data signal by differentially and integrally processing a reproduced signal etc. from a recording medium and shifting its phase by approximately 90''. 1. The input signal is current differentiated by a capacitor connected between the emitters of the second transistor, the emitter voltages of these first and second transistors are integrated by an integrating circuit, and inverted by a differential amplifier circuit. By converting the integrated current output and the above-mentioned differential current output into a current and taking it out, good integration characteristics can be obtained with a simple circuit configuration that is less susceptible to power supply fluctuations and is resistant to common mode noise. It is something.

C9 Conventional technology-i, when detecting data from a reproduced signal in a floppy disk, video tape recorder, digital tape recorder, etc., it is essential that the phase of the signal be shifted by approximately η90°. Ru.

This means that in the reproduced signal as shown in Figure 2A, "1
”, “0” information change point corresponds to the peak point of the signal waveform, for example, point 1) + % pz, etc. However, since detecting this peak point is generally troublesome, this waveform is
This is because it is necessary to transform the peak point 1)+s pi corresponding to the change point of the information as shown in FIG. B to bring it to the so-called zero cross point. By converting the signal waveform to the one shown in Figure 2B, the so-called zero cross
The original data signal can be easily obtained using a comparator or the like.

In this way, differential type detection circuits have often been used to shift the signal phase by approximately 90 degrees.
Since the frequency characteristics deteriorate in the low frequency range, so-called integral type detection circuits that use both differentiation and integration are also used. This integral-type detection circuit obtains a target output signal by combining the differentiated input signal, such as the reproduced signal, and the integrated and inverted signal at an appropriate ratio. An example is shown in FIG.

In the integral detection circuit shown in FIG.
An input signal such as the above-mentioned reproduced signal inputted to is supplied to a differentiating capacitor 33 via an emitter-follower transistor 32, so that a current signal obtained by differentiating the above-mentioned input signal flows through the capacitor 33. Further, the emitter output of the transistor 32 is integrated by an integrating circuit 34 consisting of a resistor 34R and a capacitor 34C, and is inverted and amplified by a transistor 35 to become a current output. The combined current of this inverted integral output current and the differential current is:
The output transistor 38 is converted into a voltage by flowing through the load resistor 37 of the transistor 36 having a common base configuration.
It is taken out from the output terminal 39 via.

D0 Problems to be Solved by the Invention Incidentally, in the conventional integral detection circuit as shown in FIG. 3, the load resistance 3 of the common base transistor 36
Since the output voltage of 7 is determined based on the power supply voltage Vcc, it is not only easily affected by power supply fluctuations, but also because of the so-called single-ended configuration, the common-mode noise is amplified and output as is, and the common-mode noise signal is It has the disadvantage of being weak against In addition, in order to handle signals up to a relatively low frequency range, large-capacity bypass capacitors 41, 42, etc. are required, which is not suitable for integrated circuits, increases costs, and A drawback arises in that it takes a long time for the operation to reach a steady state after returning from a standby state or the like. Furthermore, since the input impedance of the amplifier (transistor 35) that inverts and amplifies the integrated signal is low, the impedance of the integrating circuit 34 must also be low, and in this case, in order to make the integration as ideal as possible, the capacitor 34C is Requires something with relatively large capacity and high precision. .

The present invention has been made in view of these circumstances, and eliminates the above-mentioned drawbacks, is less susceptible to power fluctuations, is resistant to common mode noise, and requires a large-capacity bypass capacitor. It is an object of the present invention to provide an integral detection circuit which can handle signals in a low frequency range without any interference, can shorten the waiting time until steady operation after power-on, etc., and has a configuration suitable for integration into an integrated circuit.

Means for Solving the E0 Problem In order to solve the above-mentioned problem, the integral detection circuit according to the present invention includes first and second transistors whose bases are respectively connected to a pair of non-inverting and inverting input terminals. , a differential capacitor inserted and connected between the emitters of the first and second transistors, and a third transistor whose collectors are connected to the emitters of the first and second transistors, respectively.
A transistor differential pair consisting of a fourth transistor, and the respective emitter voltages of the first and second transistors are integrated and supplied to the bases of the fourth and third transistors of the transistor differential pair, respectively. an integrating circuit, the differential current flowing through the differentiation capacitor and the integrated current of the differential pair of transistors are added together, and an output is taken out from the collector of at least one of the first and second transistors. It is said that

By adopting an F1 action differential type circuit configuration, it is less affected by power supply fluctuations, is resistant to common mode noise, and can handle signals in the low frequency range without the need for large-capacity bypass capacitors. It is possible to shorten the waiting time for normal operation after turning on the power.

G. Embodiment FIG. 1 is a circuit diagram showing an integral detection circuit according to an embodiment of the present invention.

In FIG. 1, a reproduced signal from a magnetic disk or magnetic tape, for example, is supplied between a non-inverting input terminal 1 and an inverting input terminal 2, and these pair of non-inverting and inverting input terminals 1. 2 are connected to the bases of the first and second transistors 11 and 12, respectively. A differentiation capacitor 3 is inserted and connected between the emitters of these first and second transistors 11.12, and the input signal is differentiated by this capacitor 3, and the collector output current of each transistor 11.12 is It is taken out. Furthermore, the emitters of the first and second transistors 11.12 are connected to the collectors of the third and fourth transistors 13.14. , each emitter is grounded via a current source, and a resistor 5 is inserted and connected between these emitters, thereby forming a so-called differential amplifier configuration. Furthermore, an integrating circuit 4 is provided which integrates each emitter voltage of the first and second transistors 11.12 and supplies the integrated voltages to the respective bases of the fourth and third transistors 13.14 of the transistor differential pair. ing. This integrating circuit 4 includes a first resistor 4a having one end connected to the emitter of the first transistor 11, a second resistor 4b having one end connected to the emitter of the second transistor 12,
A capacitor (consisting of an integrating capacitor 4C) inserted and connected between the other ends of these resistors 4a and 4b connects the output from the other end of the first resistor 4a to the fourth transistor through the buffer transistor 16. The configuration is such that the output from the other end of the second resistor 4b is supplied to the base of the third transistor 13 via the buffer transistor 15.

Each emitter of the buffer transistors 15 and 16 is connected to a current source, and each collector is connected to a power supply Vcc. Further, the first and second transistors 1
Each collector of 1.12 has a load resistance of 17.18
The inverted output is taken out from the collector output terminal 7 of the transistor 11, and the non-inverted output is taken out from the collector output terminal 8 of the transistor 12.

In such an integral detection circuit, the input signal supplied to the first and second transistors 11.12 via the input terminal 1.2 is differentiated by the current differentiation capacitor 3, and the input signal is differentiated by the current differentiation capacitor 3. The collector output current is 12. At the same time, the voltage of the input signal is obtained as it is at each emitter of both transistors 11.12, and after each input signal voltage is integrated by the integration circuit 4, it is passed through the buffer of transistor 16.15 to transistor 14.13. The output of the differential amplifier is added to the respective collector currents of the second and first transistors 12 and 11. In this way, a current that is a combination of the differential current and the inverted integral current is generated by the transistor 11.
By flowing through each of the 12 load resistors 17.18, an output voltage is taken out from each output terminal 7.8.

Here, the buffer transistors 15 and 16 also have a level thick function for securing the collector-base voltage VCI of the third and fourth transistors 13 and 14.

In addition, in FIG. 1, the resistor 5 inserted and connected between the emitters of the third and fourth transistors 13 and 14 is as follows.
It is a variable resistor whose resistance value can be changed, and by adjusting this resistance value, the amount of addition of the integral signal to the differential signal is adjusted. Furthermore, although the configuration of the so-called DC bias system is omitted in FIG.
The circuit shown in the figure is a three-stage Darlington-connected differential amplifier circuit in terms of direct current, and can use the same conventional direct current bias system circuit configuration.

Since such an integral detection circuit has a differential circuit configuration as a whole, it is less susceptible to power supply fluctuations and is resistant to common mode noise. In addition, it eliminates the need for large-capacity bypass capacitors, making it suitable for IC implementation, and requires less waiting time until the operation returns to a steady state after turning on the power or returning from standby mode. , even if the capacitance value of the integral capacitor is reduced, it is possible to obtain an integral characteristic close to the ideal.

Note that the present invention is not limited to the above-mentioned embodiments, and for example, the buffer transistors 15 and 16 may not be provided in principle (or may be replaced by these transistors 15 and 16).
Level shifting diodes may be used instead of 16. In this case, the anode of each level shifting diode is connected to the integrating circuit 4 side, and the cathode is connected to the base side of each transistor 13 and 14. In addition, various changes can be made without departing from the gist of the present invention.

H1 Effects of the Invention According to the integral detection circuit of the present invention, it is less susceptible to power supply fluctuations, is strong against common-mode noise signals, and eliminates the need for large-capacity bypass capacitors. The waiting time until the operation returns to a steady state when returning from standby mode is short (it becomes possible), and even if the capacity of the integrating capacitor is reduced, ideal integral characteristics can be obtained, making it easier to integrate circuits (ICs). ), suitable for I
By using C, the number of external parts and the area occupied can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an integral detection circuit according to an embodiment of the present invention, Fig. 2 is a time chart for explaining the detection operation of a reproduced signal, etc., and Fig. 3 shows a conventional example of an integral detection circuit. It is a circuit diagram. l... Non-inverting input terminal 2... Inverting input terminal 3... Differential capacitor 4... Integrating circuit 4a, 4b... Integrating resistor 4C... Integrating capacitor 5... Integral addition ffi! J! Adjustment resistor 7...Inverting output terminal 8...Non-inverting output terminal 11...First transistor 12...Second transistor 13...Third transistor 14...Fourth transistor 15.16... Buffer transistor 17.18.
··Load resistance

Claims (1)

[Claims] First and second transistors whose bases are respectively connected to a pair of non-inverting and inverting input terminals;
a differential capacitor inserted and connected between the emitters of the transistors, and a third and fourth transistor whose collectors are connected to the emitters of the first and second transistors, respectively; Each of the above 1st
, an integrating circuit that integrates each emitter voltage of the second transistor and supplies each of the emitter voltages of the second transistor to the bases of the fourth and third transistors of the transistor differential pair, a differential current flowing through the differential capacitor, An integral detection circuit characterized in that the integrated current from the differential pair of transistors is added together and an output is taken out from the collector of at least one of the first and second transistors.