JPS63172348A - Semiconductor integrated circuit containing secret information - Google Patents

Abstract

PURPOSE:To prevent a leakage of the secred information to the persons excluding the one who set this information by using a flip-flop which is reset a 1st write signal of a secret information register and a gate which activates the read enable signal of said register only when the flip-flop is kept reset. CONSTITUTION:When a read command is supplied at the time of a test, the output of a gate 14 is active in the timing 0 since an RS flip-flop 13 is set by a power-on resetting circuit 12. Then a test data stored in a secret information register 5 in the timing 1 is delivered to a data external terminal 2. The test data is compared with the output data. When the coincidence is secured from said comparison, it is decided that the register 5 passed a shipment test. When a read command of the register 5 is supplied at the time of the user application, the output of the gate 14 is not active since the flip-flop 13 is reset by the circuit 12. Thus the contents of the register 5 can not be read. The flip-flop 13 is never set again as long as a power supply has a rise again and the contents of the register 5 are never read.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit with built-in confidential information that stores confidential information and whose contents are prohibited from being read.

2. Description of the Related Art In recent years, information systems have become increasingly decentralized, and communication networks that connect computers have come to play an important role. At the same time, maintaining confidentiality in communication channels has become a problem. As a countermeasure for this, when handling confidential information within the system, use a secret card to encrypt the information to ensure confidentiality so that even if a third party looks into the information, the meaning of the information will not be known. A method is being taken. Since the algorithms of many cryptographic systems are made public with the premise that they will be implemented on LSI, the security of the system depends on the key. Keys include session keys that are used to encrypt data and are disposable after each communication, and mask keys that are used to encrypt session keys during delivery. Not,
It should be kept secret. Therefore, the registers in cryptographic LSIs that store the contents of these keys must be designed so that they can be written to but not read out.6 On the other hand, during LSI shipping tests, the specified values are not stored in these key registers. It is necessary to read back the key register to make sure.

Shipping tests for registers (referred to as secret information registers) that store secret information and whose contents are prohibited from being read (referred to as secret information registers), such as the key register in the cryptographic LSI described above, have conventionally been carried out as follows. Please note that the explanation from here is on LS
It is assumed that the contents of internal registers can be observed only by operating the external terminals of the I package.

FIG. 2 shows a configuration diagram of an embodiment of a conventional LSI incorporating a secret information register.

1 represents an LSI package, 2 represents an external data terminal for inputting and outputting data, and 3 represents a mode terminal for setting the mode of the LSI. 4 is a control unit that generates a read signal CO and a write signal C3 for the secret information register as a result of decoding the read command and write command of the secret information register; 5 is a secret information register that stores secret information; 6 is a timing 1; A gate 7 enables writing to the secret information register 5 when Gates are shown to enable reading.

The operation of the conventional secret information register configured as described above during a shipping test will be described below.

<Writing to the secret information register> When the 1.8 secret information register write command is input, the control unit 4 generates a write signal C3.

2. At timing 1, the gate 6 becomes active, and the test data set in the data external terminal 2 at that time is stored in the secret information register 5.

<Reading the secret information register> 3. Set a test mode pattern in the mode terminal 3 that is known only to the manufacturer and secret to the user.

In the case of Figure 2, the test mode pattern is (mQ, ml,
The case where m2, m3) = (0, 1, 0, 1) is given as an example. At this time, mO to In3 are assumed to be mode terminals.

4. When the pattern set to the mode terminal is a predetermined pattern, the output of the test mode detection gate 7 becomes active.

5.8 When a read command for the dense information register is input, the control unit 4 generates a read signal Co, and at timing 0.
At this point, the output of gate No. 8, that is, the read enable signal of the secret information register becomes active.

6. The contents of the secret information register are output to the data external terminal 2.

<Comparison> The test data stored in 7.2 and the data output in 6 are compared, and if they match, the secret information register passes the shipping test.

Note that there is no need to provide a special mode terminal.
It may also be used as a terminal with other functions.

Also, for convenience of explanation, the configuration is such that the secret information register is read and written using commands from outside the LSI, but it is also possible to generate the secret information register read signal CO and write signal C3 using an external terminal signal. good.

Problems to be Solved by the Invention However, with the above configuration, no matter how long the bit width of the test mode pattern is and the pattern is determined to be difficult to expose, only one type of test mode pattern can be set in terms of hardware. , once someone other than the manufacturer obtains the test mode pattern by chance or by some other means, the secret information in all systems using this LSI will be exposed by putting the LSI into test mode. The pattern is not revealed only by chance, but is steadily made by trying all the patterns for all the external terminals. It is a fatal flaw for cryptographic LSIs that the secret information, that is, the key, in cryptographic LSIs is exposed.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a semiconductor integrated circuit with built-in confidential information in which confidential information is not exposed to anyone other than the person who sets it, and furthermore, the contents of the register can be freely tested during testing.

Means for Solving the Problems The present invention provides a secret information register for storing secret information, an external terminal for reading or writing the contents of the secret information register, and a read signal for the secret information register in response to an external command. a control unit that generates a first write signal and a second write signal; a gate that generates a write enable signal for the secret information register from the first or second write signal for the secret information register; and a gate that generates a write enable signal for the secret information register; a power-on reset circuit that generates a pulse when the power-on reset circuit generates a pulse; a flip-flop that is set by the pulse generated by the power-on reset circuit and reset by a first write signal of the secret information register; and when the flip-flop is in the set state. The present invention is a semiconductor integrated circuit with built-in secret information, characterized in that it includes a gate that activates a read enable signal of a secret information register.

Operation According to the above-described configuration, the present invention performs a test by setting test data in the secret information register using the second write command of the secret information register during a shipping test, and reading back and comparing the contents of the register using the read command. When used by a user, a value is set in the secret information register with the first write command. Then, logically, the fuse for the readout signal of the secret information register is cut off, and reading of the secret information register becomes impossible unless the power is turned on again. When the power is turned on again, the contents of the secret information register disappear, so the safety of the secret information is protected.

Embodiment FIG. 1 shows a configuration diagram of an LSI incorporating secret information in an embodiment of the present invention.

1 represents an LSI package, and 2 represents a data terminal for human output of data. 10 is a read command and a first write command (
decodes the second write command (for the user) and the second write command (for the test), and reads the secret information register read signal CO.
A control unit generates a first write signal C1 (for user) and a second write signal C2 (for test), 5 is a secret information register that stores a secret, and 11 is a timing 1 signal using C1 and 02 signals. And the first 3! A gate for activating the write enable signal of the secret information register 5 is shown. 12 is a power-on reset circuit that generates a pulse when the power is turned on; 13 is an RS flip-flop that is set by the pulse generated by the power-on reset circuit and reset by the first write signal C1 of the secret information register; 14; indicates a gate that enables reading of the secret information register when the RS flip-flop is set and a read command of the secret information register is given.

The operation of this embodiment configured as described above will be explained below separately during a shipping test and when used by a user.

First, the testing method at the time of shipment is as follows: During testing: Writing to secret information register>T1. When the power of the LSI is turned on, the power-on reset circuit 12 generates a pulse, and the RS flip-flop 13 is set.

T2. When the manufacturer inputs the second write command for the secret information register, the in section 1o outputs the second write signal C.
Generate 2.

T3. At timing 1, gate 11 becomes active, and the test data set in external terminal 2 for data at that time is stored in secret information register 5.

During a test: Read secret information register>T4.8 When a secret information register read command is input, the control unit 4 generates a secret information register read signal CO.

Since the T5-RS flip-flop 13 is set at T1, the output of the gate 14 becomes active at timing O.

T6. The contents of the secret information register are output to the data external terminal 2.

Comparison during testing> T7. The test data stored at T3 and the data output at T6 are compared, and if they match, the secret information register passes the shipping test.

Furthermore, when used by a user, reading of the secret information register is prohibited as follows.

<Writing of secret information register when using by user> Ul,
When the LSI power is turned on, power-on reset circuit 1
2 generates a pulse and the RS flip-flop 13 is set.

02. When the user inputs the first write command for the secret information register, the control unit 10 outputs the first write signal C.
Generate 1.

U3. The first write signal C1 generated by U2 is RS
Reset the flip-flop 13.

04, gate 11 becomes active at timing 1, and the test data set in the external data terminal 2 at that time is stored in the secret information register 5.

<Reading secret information register when used by user> U5.
When a read command for the 8-density information register is input manually, the control unit 4 generates a read signal CO.

U6. Since the RS flip-flop 13 has been reset by U3, the output of the gate 14 is never activated, so the contents of the secret information register 5 cannot be read.

The RS flip-flop 13 will not return to the set state unless the power is turned on again, and therefore the contents of the secret information register cannot be read.

As described above, according to this embodiment, two types of write commands are provided for the 8 secret information register, and during testing, the secret information register can be read freely using the second secret information register old command, so that the user can When using, first
The secret information register write command can be used to logically cut off the fuse of the read signal of the secret information register to prevent the contents of the secret information from being exposed to others.

In this embodiment, it does not matter whether the logic is positive or negative.

In addition, as in the explanation of the conventional example, for convenience, the configuration is such that the secret information register is read and written by commands from outside the LSI, but the readout signal CO of the secret information register and the first Write signal C
1 and the second write signal C2 may be generated.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the test data is set using the second write command of the secret information register in the test at the time of shipment, and the secret information register is tested by reading back the data. When used by a user, use the first write command of the secret information register to set the secret information, and at the same time logically cut off the fuse of the read signal of the secret information register to prevent the contents of the secret information from being exposed to others. can. Note that in practice, only the first write command of the secret information register is disclosed to the user, but even if the second test write command is used by mistake, only the user's secret information will be exposed.
Unlike in the past, all the secret information of a system using the LSI is not exposed. Therefore, the practical effects of the present invention are significant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor integrated circuit with built-in secret information according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional semiconductor integrated circuit with built-in secret information. DESCRIPTION OF SYMBOLS 1... LSI package, 2... External terminal for data, 3... Terminal for mode, 4, 10... Control unit, 5...
...Secret information register, 12...Power-on reset circuit, 13...RS flip-flop. Agent's name Patent attorney Toshio Nakao Haka 1 person co-Reading the Rare Labor Party Collection Register hs=+C2--Ministry of Box Secret Samurai Collection Sister; Inclusion Signal (for shipping test) CO - Mioshii's word c3 of the secret love story C3 - Rasta's 1! Figure 2 of the included http issue

Claims (1)

[Claims] A secret information register for storing secret information, an external terminal for reading or writing the contents of the secret information register, and a read signal, a first write signal, and a second write signal for the secret information register according to an external command. a control unit that generates a signal; and a first controller of the secret information register.
Alternatively, a gate that generates a write enable signal for the secret information register from the second write signal, and a power-on reset circuit that generates a pulse when the power is turned on;
A flip-flop is set by the pulse generated by the power-on reset circuit and reset by the first write signal of the secret information register, and a read enable signal of the secret information register is activated only when the flip-flop is in the set state. What is claimed is: 1. A semiconductor integrated circuit with built-in secret information, characterized in that it is equipped with a gate that enables