JPS63171037A - Reception equipment with collision detecting function - Google Patents

Abstract

PURPOSE:To surely and efficiently detect collision independently of the collision phase by sampling outputs of two comparing circuits different in threshold by clocks different in phase and providing a delay circuit in the succeeding stage of one code rule illegality detecting circuit. CONSTITUTION:The output of a partial response filter 11 is given to a comparator 12 having a threshold slightly higher than the zero level and a comparator 13 having a threshold slightly lower than the zero level. Outputs of comparators 12 and 13 are sampled in shift registers 15 and 19 by clocks whose phases are made different from each other by a phase shifting circuit 23. Outputs of registers 15 and 19 have code rule illegal patterns detected by code rule illegality detecting circuits 25 and 26. Outputs of circuits 25 and 26 are given to a collision deciding circuit 29 through an OR circuit 28, and the circuit 29 counts the number of pulse of circuits 25 and 26; and if the counted value exceeds a prescribed value, collision is decided to output the detection signal. A delay circuit 27 is provided following the circuit 25 to avoid overlap between outputs of circuit 27 and 28, and collision is efficiently detected.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention uses the C3MA/CD method (
Carrier 5ense Multiple
Access With Co11ision Det.
The present invention relates to a receiving device with a collision detection function that performs collision detection as well as data transmission in a bus-type local network using a bus-type local network using the EC method.

[Conventional technology]

In Fig. 5, considering the Gwipulse code as a 1B2B code,
As an example of application to optical transmission, for example, ``Study of 32 Mb/S optical star transmission system using csMA/CD control'' (1 published in Subsidiary Communications Society Technical Research Report C583-110,
1 shows a transmitting/receiving system including a conventional receiving device with a collision detection function shown in 1983).

In the figure, (1) is a transmitting device, (2) is a GUI pulse encoding circuit, (3) is a light emitting element drive circuit, (4) is a light emitting element, (5) is an optical fiber, (6) is an optical star coupler,
(7) is an optical fiber, (8) is a receiver, (9) is a light receiving element, (1o) is a front-end amplifier circuit, (11) is a partial response (1°-1) filter (hereinafter referred to as PR(1, -1
) abbreviated as filter. ), (12) is the first comparison circuit, (
14) is the timing extraction circuit, (15) is the first shift register, (16) is register 1, (17) is register 2, (18) is register 3, (24) is the block synchronization circuit, (25) is The first code rule violation detection circuit (hereinafter abbreviated as the first CRV detection circuit) (29) is a collision determination circuit.

Fig. 6 is a waveform diagram of each part of a conventional receiver with a collision detection function. The optical signal (hereinafter abbreviated as collision signal), (lla) is the partial response (1, -1) filter output of the main signal (hereinafter abbreviated as main signal PR (1, -1) filter output), (
1l b> is the partial response of the collision signal (1, -
1) Filter output (hereinafter abbreviated as collision signal PR (1, -1) filter output), (llc) is the partial response (1, -1) filter output (hereinafter referred to as signal collision signal) that combines the main signal and collision signal PR(1,-1) is abbreviated as filter output), (12a) is the first comparison circuit output, (14a)
is the first clock, (16a) is the register 1 output, (2
5a) is the output of the first code rule violation detection circuit (hereinafter referred to as the first C
(abbreviated as RV detection circuit output), (30) is the + side threshold, (
31a) and (3lb) are the sample phases of the first clock.

Figure 7 is a phase relationship diagram between the main signal and the collision signal. When PR(1,-1) filter output eye pattern, (
11f> is PR(1,-) when the phase difference with the main signal is -
1) Filter output eye pattern, (31) is the sample phase of the first clock.

FIG. 8 is an explanatory diagram showing the code rules for each part in a conventional receiver with a collision detection function.

Next, the operation will be explained. The signal flow will be explained using FIG. In the transmitting device (1), the bucket transmission data is encoded (0-10, 1-
01) After that, the light emitting element (4) is intensity-modulated by the light emitting element driving circuit (3) and output as an optical signal to the optical fiber (5). The output signal of the optical fiber (5) is input to the optical star coupler (6). The optical star coupler (6) outputs the input optical signal to each output optical fiber including the optical fiber (7) as an optical signal of equal level. The output of the optical fiber (7) is input to a light receiving element (9) of a receiving device (8) and converted into a photoelectric signal. The output signal of the light receiving element (9) is amplified by the preamplifier circuit (1o) and then passed through the PR (1, -1) filter (1o).
1) is input.

The operation after the PR(1,-1) filter (11) will be explained using FIG. In the figure, it is assumed that a collision signal (10b) is received while the main signal (10a) is being received. PR (1
, -1) has the function of subtracting the filtered signal (11). The output of the PR (1°-1) filter (11) is 1la) for the main signal (10a), and the collision signal (10b).
(IIC), and the waveform at the time of collision is a combination of both (IIC).

PR<1. -1) A method of detecting a collision from the output of the filter (11) will be explained using FIG. Transmission data is classified into four types of 2-bit data.

After Gwipulse encoding, PR(1,-1) filter (11
) is converted into a ternary waveform (AC waveform in the sense that it has + and - amplitudes). The zero level of the ternary waveform is "0", which is created by subtracting 0 and O, and "0ne", which is created by subtracting 1 and 1, in the dipulse encoder. The first comparison circuit (12) identifies ternary waveforms with a threshold (30) shifted slightly above the zero level. The output of the first comparator circuit (12) when there is no collision is at a frequency of 2f.

It samples with the first clock (14a) of [Hz] and stores three consecutive bits in the first shift register (15). Register 1 (16) of the first shift register (15)
The waveform of the output Q of ) is shown in (16a) in FIG. 8th
The figure shows the outputs Q+ of register 1 (16), register 2 (17), and register 3 (1B) corresponding to the sample results of the PR (1, -1) filter (11) output,
Q4 and Q.

shows. When a collision occurs, a zero level is transferred onto the threshold (30) by the collision signal and the first comparator circuit (12)
detects this and outputs (12a) in FIG. In FIG. 8, the second Q in the 3-bit series
2 is shown as a 3-bit sequence that violates the coding rule.

When a negative level occurs in the output of the PR (1, -1) filter (11), it is easy to detect a 3-bit sequence that violates the coding rule even if the collision signal level is small. First CRV detection circuit (
25) determines whether or not there is a violation of the coding rule for each first shift register, and if a violation of the coding rule is detected, the process shown in FIG.
The detection pulse shown in a) is output to the collision determination circuit (29).

□ The code rule violation detection clock with a period of [seconds] is output from the second register (17) of the first shift register (15) by the block synchronization circuit (24) immediately after the start of reception of the main signal (10a). Q2 has a PR (1, -1) filter (1
1) The sample result for the zero level of the output is synchronously pulled into the output phase, and is thereafter held at this phase and output.

In Figure 8, there are two types of zero level: “0” and @0ne, but “0ne” is 1 and 1 (ON and ON of optical signal).
This is generated due to the subtraction of , and there is a lot of shot noise in the light receiving element (9) (because it occurs, the code rule violation is likely to occur due to the noise even when there is no collision, so it is better not to use it for collision detection.Hereafter, it will be referred to as "0 tree". The following description assumes that violations of the coding rules that occur in the above are ignored.

A collision determination circuit (29) counts the number of output pulses of the CRV detection circuit (25), and when the count value exceeds a specified value, it determines that a collision has occurred and outputs a detection signal.

Next, a case in which it is difficult to detect a collision in a conventional receiver with a collision detection function will be explained using FIG. (11d)
is the eye pattern of the main signal at the output of the PR(1,-1) filter (11). After identification by the first comparator circuit (12), the second register (
16), the phase (31) sampled by the first clock of frequency 2ro [Hz] is shown in the figure. (11e) is an eye pattern of a signal that collides with the main signal with a phase difference of 0 (encoding block boundaries overlap).

The zero level of the main signal due to the collision is transferred to ±h saw. The first comparison circuit (12) detects a violation of the sign rule when transferred to the + side, but cannot detect it when transferred to the - side. '(llf) collides with the main signal due to the phase difference -. This is the eye pattern of the signal. The zero level of the main signal due to the collision is transferred by ±hmin. In this case, detection may be missed because the amplitude transferred to the + side is small.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional receiver with a collision detection function, there is only one comparison circuit that detects fluctuations due to zero-level signal collisions, and there is also one collision sampling point, so depending on the collision phase, zero-level signal collisions may occur. The disadvantage is that the level transfer amount is small and collision detection is likely to be missed.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a receiver with a collision detection function that can improve the deterioration of collision detection characteristics due to collision phases.

[Means to solve the problem]

The receiving device with a collision detection function according to the present invention has PR(1,
-1) The second comparator circuit has a threshold value below the zero level generated in the filter output, and the second comparator circuit output has a frequency of 2fe [Hz] and a clock with a first frequency of 2fo [Hz]. a second CRV detection circuit that detects a code rule violation from a 3-bit sequence in the second shift register; □f the circuit output
.

C seconds] A delay circuit that delays the clock, an OR circuit that receives the output of the second (or first) CRV detection circuit, and the output of the delay circuit as inputs is added, and the output of the OR circuit is used as the input of the collision determination circuit. .

[Effect]

The receiving device with a collision detection function according to the present invention has a PR (1'
, -1) The first and second comparator circuits have thresholds above and below the zero level generated in the filter output, so that the transfer of the zero level due to collision is above.

Make it possible to detect whichever is below. Also, the first
and the frequency 2r of the second shift register.

By providing a difference in the clock phases of [Hz], even if the amount of transfer of the main signal zero level in one clock phase is the minimum, a larger amount of capture can be obtained in the other clock phase.

Furthermore, since the phases of the first and second clocks with a frequency of 2ro [Hz] are different, two CRV pulses may be generated in the same bit. so that it can be counted as
Delay the output of the first (or second) CRV detection circuit by □ [seconds] and perform a logical sum f.

After that, it is input to the collision determination circuit. By the means described above, it is possible to improve the missed collision rate.

[Embodiments of the invention]

FIG. 1 shows the configuration of a transmitting/receiving system including an embodiment of a receiving device with a collision detection function according to the present invention.

In Figure 5, parts with the same symbols as in Figure 5 indicate the same parts, (13) is the second comparison circuit, (19) is the second shift register, (20) is register 4, and (21) is the register. 5 and (22) are registers, and registers 6 and (26) are second code rule violation detection circuits (hereinafter abbreviated as second CRY detection circuits).
, (27) is a delay circuit, (2nd) is an OR gate, (23)
) is a phase shift circuit.

FIG. 2 is a waveform diagram of each part of the receiver with collision detection function shown in FIG. 1 when a bi-phase code is considered as a 1B2B code. In the figure, (13a) is the output of the second comparison circuit, ( '20a) is register 4 output, (26a
) is the second coding rule violation detection circuit output (hereinafter referred to as second CRV
(abbreviated as detection circuit output) (27a) is the delay circuit output, (
24a) is the block synchronization circuit output, (28a) is the OR circuit output, (32) is the negative threshold, (33a), (33b)
) is the first clock, (34a), (34b) are the second clock
are each sample phase of the clock.

Figure 3 is a phase relationship diagram between the main signal and the collision signal. In the diagram, (11f) is the PR (1, -1) filter output of the collision signal at the phase where signal collision at the + side threshold is most difficult to detect. The eye pattern (11g) is the PR (1, -1) at the phase where the collision signal is most difficult to detect at the - side threshold.
The filter output (32) is the negative threshold.

Next, the operation will be explained. In FIG. 1, the receiving device with a collision detection function according to the present invention includes a second comparator circuit (13), a second shift register (19) (
Register 4 (20), Register 5 (21), Register 6
(22)), a second CRV detection circuit (26), a delay circuit (27), an OR circuit (2B), and a phase shift circuit (23); the other parts operate in the same way as before. I do.

In Figure 1, the output of the PR(1,-1> filter (11) is input to the second comparator circuit (13).The second comparator circuit (13) outputs the PR(1,-1) filter. The second shift register (19) has a threshold slightly below the zero level of , and detects when the zero level is shifted downward due to signal collision.The second shift register (19) uses the frequency 2ro output from the timing extraction circuit (14) Sample the output of the second comparator circuit (13) with a second clock obtained by delaying the first clock of [Hz] by τ [seconds] by the phase shift circuit (23),
A consecutive 3-bit sequence is stored in the second shift register (19). The second CRV detection circuit (26) uses the output Q4 of the second register (20), the output Q3 of the second register (21), and the output Qh of the third register (22) of the second shift register (19). Detect coding rule violation patterns.

FIG. 2 shows a method for detecting a code rule violation pattern.

This will be explained using FIG. PR(1,-1) filter (
11) The operation of the first comparator circuit (12) having a threshold value on the + side of the output zero level is a conventional example (FIG. 6).

Figure 8). PR(1,-1) filter(1
1) The second comparator circuit (13) has a threshold value (32) on one side of the output zero level, so that the zero level reaches the threshold value (32) due to the collision signal.
32) is detected, and (13a) in FIG. 2 is output. In FIG. 4, a case where a change occurs in the second Q in a 3-bit sequence is shown as a 3-bit sequence that violates the coding rule. As mentioned above, P
R(1,-1) filter (11) output above zero level.

By providing comparison circuits (12) and (13) with threshold values below, the zero level is raised by the collision signal.

Violation of the coding rules can be detected no matter where the money is transferred.

Next, the frequency 2f is input to the first shift register (15) and the second shift register (19).

The effect of giving a difference to the [Hz] clock phase will be explained using FIG. 3. In FIG. 3, the sampling point (34) of the second shift register (19) is the sampling point (33) of the first shift register (15).
It is delayed by τ [seconds]. (Ilf) is an eye pattern of a collision signal that collides at the phase where the amplitude is at the minimum value at the sampling point (33) of the first shift register. At the first sampling point (33), collisions are likely to be missed as in the conventional case. However, at the second sampling point (34), a large collision signal amplitude (ht) is obtained at this time, making it possible to easily detect the collision. (
11g) is the sampling point of the second shift register (
34) is a collision signal eye pattern in which the collision signal amplitude reaches its minimum value. In this case, the sampling point (3
4), collisions are missed, but sampling point (3)
In 3), the sampling point is set to the first one so that a large collision signal amplitude (ht) can be obtained and collision detection can be easily performed.
shift register (15) and second shift register (1
By providing a difference in 9), it is possible to improve the possibility of overlooking collisions. Note that since the zero level "0" (generated from subtraction of 0 and 0) of the output of the PR (1, -1) filter (11) is an upward-sloping waveform, the first comparator circuit (which has a threshold on the + side)
12) A first shift register that samples the output (
It is advantageous to set the clock of 15) to a phase that is more advanced than the clock of the second shift register (19) which samples the output of the second comparator circuit (13) which has a threshold value on one side, since it is less likely to cause false collision detection. be.

Next, the effect of the delay circuit (27) will be explained using FIG. 2. In Figure 2, the PR(1,-1) filter (
11) Main signal at the output (11) At this time, the first comparison circuit (12) and the second comparison circuit (13) are at the sampling point (33a).

At (34a), it is detected that the zero level is transferred beyond the thresholds (30) and (32) by the collision signals, respectively. The outputs Q, ,Q, of the first shift register (15), the register (16) of the second shift register (19), and the register 4 (20) are (16a),
(20a).

The first CRV detection circuits (25) and (26) detect the cycle of the output from the block synchronization circuit (24). The CRV detection pulse is output in the same time slot (
25a, 26a). If the CRV number is counted in the collision determination circuit (29) by taking the logical sum as it is, only one will be counted, and collision detection will be delayed. Delay circuit (27
) is the output of the first CRV detection circuit (25) □ [seconds]
Since the output is delayed, the CRV number is determined by the collision detection circuit (29)
Even if the smell is delayed, the next CRV pulse will occur in 2
Since it is the time slot destination (because CRV is not detected in the "0*" part), there is no overlap.

When the sample phases of the first shift register (15) and the second shift register (19) are in the same phase, the CRV pulse is output from only one of the CRV detection circuits, so the delay circuit There is no effect of (27).If a difference is given to the sample phase of the first shift register (15) and the second shift register (19), 2
CRV pulses may be output simultaneously from two CRV detection circuits, and the effect of the delay circuit (27) is exhibited.

The above explanation deals with the case where the sampling phase of the first shift register (15) is earlier than the sampling phase of the second shift register (19), but conversely, the sampling phase of the first shift register (15) is earlier than the sampling phase of the second shift register (19). A similar effect can be obtained even when the sampling phase is later than that of the second shift register (19).

〔Effect of the invention〕

As described above (according to the present invention), by sampling the first comparator circuit output and the second comparator circuit output with two clocks having different phases, reliable collision detection can be performed regardless of the collision phase. By placing the delay circuit after the first CRV detection circuit or the second CRV detection circuit, C
This prevents RV pulses from overlapping and enables efficient collision detection.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram showing one embodiment of the present invention, and Fig. 2 is a block diagram showing an embodiment of the present invention.
The first point when considering a pi-phase code as a B2B code
FIG. 3 is a diagram of the phase relationship between the main signal and the collision signal, and FIG. 4 is a code rule for each part of the receiver with collision detection function according to an embodiment of the present invention. 5 is a configuration diagram showing a transmitting and receiving system including a conventional receiver with a collision detection function, and FIG. 6 is an explanatory diagram showing 1.
The fifth point when considering a biphase code as a B2B code
Waveform diagram of various parts of receiving bag H with collision detection function shown in figure 7.
FIG. 8 is a phase relationship diagram between a main signal and a collision signal, and FIG. 8 is an explanatory diagram showing each part in a conventional receiver with a collision detection function by reference numeral. In the figure, (1) is a transmitting device, (2) is a 1B2B code circuit, (3) is a light emitting element drive circuit, (4) is a light emitting element, (8
) is a receiving device, (9) is a light receiving element, (10) is a preamplifier circuit, (11) is a partial response (1, -1) filter, (12) is a first comparison circuit, (13) is a Second comparison circuit, (14) is a timing extraction circuit, (15) is the first shift register, (19) is the second shift register, (24) is the block synchronization circuit, (25) is the first code (26) is a second sign rule violation detection circuit, (23) is a phase shift circuit, (27) is a delay circuit, (28)
) is an OR circuit, and (29) is a collision determination circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Patent Attorney Muneharu Sasaki Figure 2 Figure 4 Figure 6 Figure 5a1 Figure 7;

Claims (1)

[Claims] Packet transmission data with a bit rate of f_o [bits/second] is converted into a 1B2B code and then intensity-modulated, and a transmitted signal is received, and the received signal is converted from the received signal to 1/2f_
a partial response (1, -1) filter that performs AC conversion by subtracting a signal delayed by o [seconds];
a first comparison circuit that receives the output of the partial response (1, -1) filter as an input and identifies a signal using a threshold that is slightly higher than the zero level of the output of the partial response (1, -1) filter; Said Partial Respons (
1, -1) A second comparator circuit that identifies a signal with a threshold slightly lower than the zero level of the filter output, and the output of the first comparator circuit with a first clock having a frequency of 2fo [Hz]. A first code rule violation detection circuit monitors the continuous 3-bit pattern obtained after sampling at a period of 1/f_o [seconds] to detect code transition rule violations, and the output of the second comparison circuit is connected to the frequency is 2f_o [Hz] and is sampled with a second clock having a phase different from the clock of the first frequency 2f_o [Hz], and the continuous 3-bit pattern obtained after sampling is monitored at a period of 1/f_o [seconds]. a second coding rule violation detection circuit that detects a code transition rule violation; a delay circuit that receives the output of the first or second coding rule violation detection circuit and has a delay time of 1/f_o [seconds]; The delay circuit output is used as the first input, and the second
Or a receiving device with a collision detection function, comprising: an OR circuit whose second input is the output of the first coding rule violation detection circuit, and outputs the output of the OR circuit as a collision detection signal.