JPS63169856A - Carrier recovery circuit - Google Patents

Abstract

PURPOSE:To ensure the stable operation without giving disturbance to a VCO by preparing at least two kinds of synchronizing pull in signal point patterns and using the inter-code interference quantity so as to designate the synchronizing pull in signal point pattern and applying the normal synchronizing pull in only to the coincident pattern. CONSTITUTION:As the inter-code interference quantity is large, patterns P1-P3 of less signal point are adopted and the inter-code interference quantity is reduced and the pattern having much signal point is adopted sequentially. Thus, the patterns P1-P3 are the synchronizing lock signal point patterns and a pattern 4 is a normal signal point pattern. Reception data ID, QD are inputted to a ROM 11, and only when the signal comes to the signal point specified the designated signal point pattern, a specific signal display signal Sb with logic H is outputted from the ROM 11. AS to the signal point not selected, the phase lock control is stopped. In repeating the cycle above, the inter-code interference quantity is decreased gradually and then the synchronizing locking is established completely finally and the normal data demodulation is attained by the signal point pattern P4, 12, inter-code interference quantity monitor.

Description

[Detailed Description of the Invention] [Summary] This is a carrier wave regeneration circuit that performs all-point control targeting all signal points in a signal space and selection control targeting a predetermined specific signal point using a ROM. This shall be done by selecting one of a plurality of signal point patterns held in
By selecting the signal point pattern according to the amount of intersymbol interference, it is possible to perform fine control during the transition from synchronization pull-in to synchronization establishment, and achieve quick and stable carrier wave regeneration. I can do it.

[Industrial application field]

The present invention relates to a carrier recovery circuit.

A signal sent out from the transmitting side after being subjected to phase modulation based on digital data is applied to a demodulator as a received modulation signal at the receiving side. This demodulator first performs synchronous detection on the received modulated signal and converts it into a baseband signal. Since this synchronous detection requires a reference carrier wave, the carrier wave regeneration circuit is used to recover and extract this from the received modulated signal.

Unless synchronization is established between the reference carrier wave obtained by carrier wave regeneration and the received modulated signal, the reference clock will not be established, and therefore normal data reproduction cannot be performed. Therefore, it is important to establish this synchronization quickly and stably.

FIG. 5 is a block diagram showing the general configuration of a demodulator. A typical demodulator 1 receives a quadrature-phase modulated signal and performs certain processing to obtain demodulated data D. After being received by the antenna and passing through a down converter, the received modulated signal Sr in the IF band is sent to a hybrid circuit (HYB) 2 where it is divided into an I channel (I-ch) signal system and a Q channel (I-ch) signal system with a phase shift of π/2. Q-ch) signal system, and after becoming a baseband signal in balanced mixers 3I and 3Q, for example, a low-pass filter, a transversal equalizer (EQL) 4I, 4Q, and an analog/ Digital converter (A/D) 5 I.

It becomes demodulated data D via 5Q.

The balanced mixers 31 and 3Q perform synchronous detection, and what is essential for this purpose is the reference carrier wave RC. The carrier wave regeneration circuit described in the present invention reproduces this reference carrier wave RC from the demodulated data D. The Costas type carrier wave regeneration processing circuit 7 and the VCO (voltage controlled oscillator) 8 in the figure correspond to the carrier wave regeneration circuit. In addition, VC
The VCO control signal to O8 is provided via a low pass filter. The reference carrier wave RC thus obtained is given to the synchronous detection section (31, 3Q, 9). 6 is a bit timing regenerator (BTR), which generates the reference clock CLK mentioned above.

[Conventional technology]

The number of signal points arranged in a signal space (a two-dimensional space defined by orthogonal r (inphase) channel axes and Q (quadrature) channel axes) is, for example, 4.
In phase PSK, it is 4 points. However, in recent years, ultra-large capacity data transmission has become necessary, and multilevel QAM (quadr
a ture amplitude modulation
n) has been put into practical use.

In this case, the number of signal points reaches 256.

The carrier wave regeneration circuit plays an extremely important role when starting data transmission or when restarting data transmission after the line condition has deteriorated due to fading or the like. In this case, the carrier regeneration circuit performs one signal point 1 obtained from the received modulated signal.
A reference carrier wave is generated by a free voltage controlled oscillator (VCO) to make the phase shift zero with one controlled object. For this reason, for example, in a 256-value CAM, all 256 signal points are processed one by one.

Such a method has the disadvantage that it takes a long time to establish synchronized pull-in, and the disadvantage that it may become stable in a pseudo-pull-in state. In order to eliminate this inconvenience, a system was proposed in which the system is switched to two stages: all-point control and selective control. In this method, V
The control voltage of the CO is monitored, selective control is performed at the start or restoration of data transmission, and the control is switched to normal all-point control after almost synchronization is established.

[Problem that the invention seeks to solve]

In the conventional method described above, since the control voltage of the VCO is monitored, selective control is started when the VCO itself becomes out of synchronization.
There is a problem that the effect of adopting selective control is not noticeable because there is an urgent need to rebuild one's own out-of-synchronization. In addition, the signal point pattern for selection control is fixedly determined in advance, and it is not possible to change it freely, and there is a problem that adaptive selection control according to line conditions is also impossible.

The present invention has been developed in view of the above problem, and it is possible to quickly enter selection control when the line condition worsens, whether at the start of data transmission or when data transmission is restored. The purpose of this invention is to propose a carrier regeneration circuit that can set the selection control mode to the optimum mode depending on the situation, and therefore has excellent operational stability.

[Means for solving problems]

FIG. 1 is a block diagram showing the basic configuration of a carrier recovery circuit according to the present invention. This carrier regeneration circuit 10 includes a ROM (read-on-litter) that holds a plurality of types of signal point patterns.
y memory) 11, a pattern specifying section 12 that specifies one of the signal point patterns according to the amount of intersymbol interference of the demodulated data D, and a pattern specifying section 12 that receives the demodulated data D and performs a logical operation thereon to generate a reference carrier RC. A Costas type carrier wave regeneration processing section 13 generates a VCO control signal S4 to be sent to the VCO 15 and a signal point display signal S indicating that each signal point of demodulated data D exists, and the demodulated data D is used as an address input, and the above-mentioned A specific signal display signal S5 indicating that the specified signal point pattern matches is read out from the ROM 11 and used as one input, and the signal point display signal S is used as the other input to generate a pattern match detection signal indicating that these match. A pattern-defeat detection unit 14 that outputs Sc, passes the VCO control signal S4 when the pattern match detection signal Sc is present, and detects the immediately preceding VC when the pattern match detection signal Sc is absent.
Passing/holding section 16 that holds the O control signal Sd
It consists of

[For production]

The magnitude of the intersymbol interference amount indicates the magnitude of the bit error rate of the demodulated data D, and is a barometer indicating the quality of the line condition. Therefore, first, as the plurality of types of signal point patterns to be stored in the ROM 11, there are at least two types of signal point patterns: a normal signal point pattern that specifies all signal points, and a signal point pattern that specifies signal points that gradually decrease from all signal points. A synchronization pull-in signal point pattern is prepared, and the larger the amount of intersymbol interference, the fewer signal points the synchronization pull-in signal point pattern is specified, and only those that match this specified signal point pattern are normally Performs synchronous pull-in.

If they do not match, the previous VCO control signal is used as is to perform normal synchronization pull-in. In this way, fine-grained synchronization pull-in control is performed, and since the signal point pattern gradually changes from a coarse signal point pattern to a fine signal point pattern, the VC
Stable operation is ensured without causing any disturbance to O.

[Embodiment] FIG. 2 is a diagram showing an embodiment of a carrier wave regeneration circuit according to the present invention. Note that components similar to those already described are designated with the same reference numbers or symbols. Demodulated data D from analog/digital converters (A/D) 5I and 5Q (Fig. 5) is ■-ch data ID and Q-ch data Q.
D, these are once flip-flops (FF) 2
Set to 1. This is for waveform shaping. In addition, I
Each of the D and QD transmission lines consists of a bus (indicated by diagonal lines), and in the case of a 256-value CAM, each consists of a 5-bit bus. Demodulated data ID and QD
is further applied to ROM 11 and becomes its address input. As described above, a plurality of types of signal point patterns are held in the ROM 11. Since this signal point pattern is important, we will briefly refer to FIG. 3 to explain it.

FIG. 3 is a diagram showing examples of various signal point patterns in the signal space. In this figure, four types of signal point patterns P1. P2
．． P3 and P4 are shown. All of these signal point patterns are defined within a signal space, and each signal space is defined by two orthogonal I-ch and Q-ch axes.
It is a dimensional space. If four-phase PSK is adopted, demodulated data will appear exactly at one of the four hatched points in the signal point pattern P1. That is, counterclockwise from the upper right point (1, 1), (0, 1), (
0°0) and (1, O) are assigned. In this embodiment, a 256-value CAM is taken as an example, and each signal point pattern is defined by 256 signal points. The signal point pattern P4 specifies all of these 256 signal points, and is employed during normal data transmission without fading. In this signal point pattern, the number of signal points gradually decreases from P4 toward Pl. In this gradual reduction, it is preferable that the signal points remain symmetrical to the origin (the intersection of the 1-ch axis and the Q-ch axis). This is to obtain phase information evenly.

In the present invention, the larger the amount of intersymbol interference, the fewer signal points patterns PL, P2. P3 or the like is adopted, and patterns with a large number of signal points are sequentially adopted as the amount of intersymbol interference decreases. This allows quick and stable synchronization pull-in. Therefore, patterns PI, P2. P3 is a signal point pattern at the time of synchronization pull-in, and pattern P4 is a signal point pattern at normal time. Note that in this embodiment, the pattern can be changed in three stages, so pattern P2. Although only P3 and P4 are adopted, PI may be inserted or replaced with other patterns, and the number of select mode stages may be increased or patterns may be increased.

A 2-bit signal is sufficient for specifying signal point patterns P2, P3 and P4, P2 is (H, H) and P3 is (
H, L), and P4 can be specified as (L, L). Returning to FIG. 2, these 2-bit signals are the 2-bit signals SMI and SM2 from the intersymbol interference amount monitor forming the pattern specifying section 12. For example, the 6th bit data (I Db
, QD&) are generated as pseudo-error pulses. The amount of intersymbol interference is almost proportional to the bit error rate (BER), and as shown in FIG. 4D, for example, when three stages of control are considered, BER-5 can be set as a threshold value.If the BER is 5X10-3 or less, it is normal, and the 2-bit signal becomes (L, L) (specify P4).

BER deteriorates from 5X10-" and BER-5xlO-"
If it is between , the 2-bit signal is (H, L) and designates P3. When the BER exceeds 5xio-'', the line condition is quite poor, and the 2-bit signal takes (H, H), specifying pattern P2.

In this case, the mode (L, H) cannot be taken, so
exclude.

The received data ID and QD are input to RO1'l 11,
Only when the signal point falls on a signal point specified by a designated signal point pattern (for example, P2), the ROM 11 outputs a specific signal display signal Sb of logic H. This is applied to one input of an AND gate 23 forming the pattern matching detection section 14. The other input of the AND gate 23 receives the signal point display signal S from the Costas type carrier wave regeneration processing section 13;
is applied.

A pattern match detection signal Sc (logical H) is sent out from the AND gate 23 forming the pattern match detecting section 14 at the timing when the logic H signals S and S appear. The presence or absence of this signal Sc determines the reference clock CLK (B in Figure 5).
(output from TR) is taken into the passage/holding section 16, or taken in is stopped.

The Costas-type carrier wave regeneration processing section 13 consists of two EXOR gates, and converts the first bit (IDI) and fifth bit (ID5) of 5-bit (256 values) I channel data.
) and the first bit (CDI) and fifth bit (QD5) of 5-bit Q channel data are input. Note that each first bit is a bit indicating polarity, and each fifth bit is a bit indicating a so-called error signal. These bits are operated by exclusive OR, and one side sends out the VCO control signal Sa, and the other side sends out the already mentioned signal point display signal Sa. The above operation is similar to that of a general Costas type carrier wave regeneration circuit. VCO control signal S4 sent here
is not always sent to the VCO 15 (via the low-pass filter 22). Every time demodulated data ID, QD is received, the processing unit 13 sends a signal point display signal S indicating that the demodulated data has fallen to a certain signal point, although it is not known which signal point it is. Of these, only those that match the signal point pattern are extracted as pattern matching detection signals Sc, and are sent to the AN in the passing/holding section 16.
A reference clock CLK is sent out from the D gate 24 to trigger a flip-flop (FF) 25. Here, a VCO control signal S4 is set in a flip-flop (FF) 25 only for demodulated data having signal points matching the signal point pattern, and the data is passed to the VCO 15. VCO1
5 outputs a reference carrier wave RC (though not yet synchronized) under the control of the signal S4, and a synchronous detection section (3I in FIG. 5).

3Q, 9) is driven.

For demodulated data having signal points that do not match the signal point pattern, the specific signal display signal Sb from ROM 11
becomes logical, the pattern matching detection signal Sc also becomes logical, and the reference clock CLK is stopped by the AND gate 24. Then, since the flip-flop 25 is not triggered, it continues to hold the previous VCO control signal Sa. In other words, phase synchronization control is suspended for signal points that are not selected. Note that the FF 25 is composed of a plurality of stages of series FFs in order to match the timing of generation of the signal Sc and reception of the signal S4. In this way, the VCO 15 outputs the reference carrier wave RC that has been synchronized, for example, according to the signal point pattern P2, and thereby the demodulated data ID and QD that have been synchronously detected are obtained.

When such a cycle is repeated, the amount of intersymbol interference gradually decreases, and next, instead of signal point pattern P2, signal point pattern P3 is designated by the intersymbol interference amount monitor (pattern specifying unit 12). This time, the VCO 15 outputs a reference carrier wave RC that enables more accurate synchronization under this pattern P3. Finally, synchronization is completely established and normal data demodulation operation begins with signal point pattern P4.

4A and 4B are diagrams showing detailed examples of the carrier recovery circuit according to the present invention. Of these, the parts essential to the present invention are indicated with the same reference numbers or symbols as used in FIG. 2, and the other parts are not directly related to understanding the present invention, so their explanation will be omitted. . Furthermore, neither the low-pass filter 22 nor the VCO 15 in FIG. 2 are shown in this figure. Figures 4A and 4B are connected to each other at ■2■, ■ and ■.

〔Effect of the invention〕

As described above, according to the present invention, a carrier wave regeneration circuit that is finely controlled from the time of synchronization pull-in to the time of synchronization establishment (normal time), and therefore has high operational stability, is realized. Also, although this example describes a 256-value CAM, other CAMs may also be used.
For example, 4-value CAM (4-phase PSK), 16-value QAM, 6
Similar adaptation is possible for 4-level QAM.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle configuration of a carrier wave recovery circuit according to the present invention, FIG. 2 is a diagram showing an embodiment of the carrier wave recovery circuit according to the present invention, and FIG. 3 is a diagram showing various signal point patterns in a signal space. 4A and 4B are diagrams showing detailed examples of the carrier recovery circuit according to the present invention; FIG. 4C is a diagram showing a pseudo error rate detection circuit; FIG. 4D is a select mode switching cycle diagram; FIG. 5 is a block diagram showing the general configuration of a demodulator. DESCRIPTION OF SYMBOLS 10... Carrier wave regeneration circuit, 11... ROM, 12... Pattern specifying part, 13... Costas type carrier wave regeneration processing part, 14...
・Pattern match detection unit, 15...VCO<voltage controlled oscillator), 16...passing/holding unit, D...demodulation data, S,...signal point display signal, Sb...specific signal Display signal, Se...Pattern match detection signal, S...VCO control signal, RC...Reference carrier wave.

Claims (1)

[Claims] 1. A normal signal point pattern that specifies all the signal points in the signal space, and at least two types of synchronization pull-in signal point patterns that specify signal points that gradually decrease from all the signal points. ROM (read only memory) (
11), and a pattern that detects the amount of intersymbol interference of demodulated data (D), and specifies a signal point pattern with a smaller number of signal points as the amount of intersymbol interference increases, to the ROM (11). A designation section (12) and a logical operation are added to the demodulated data (D) to generate a reference carrier wave (
VCO (voltage controlled oscillator) (15) that sends out RC)
VCO control signal (S_d) and demodulated data (D
), a Costas-type carrier wave regeneration processing unit (13) that generates a signal point display signal (S_d) that displays each signal point of The above-mentioned RO
A pattern matching detection signal (S_
c), and when the pattern match detection signal (S_c) is output, the VCO control signal (S_d) is passed through, and when the pattern match detection signal (S_c) is not output, the immediately preceding VCO control signal (S_d) is passed. 1. A carrier wave regeneration circuit characterized by comprising a passing/holding section (16) that holds the carrier wave (16) as it is.