JPS63168700U - - Google Patents
Info
- Publication number
- JPS63168700U JPS63168700U JP6097587U JP6097587U JPS63168700U JP S63168700 U JPS63168700 U JP S63168700U JP 6097587 U JP6097587 U JP 6097587U JP 6097587 U JP6097587 U JP 6097587U JP S63168700 U JPS63168700 U JP S63168700U
- Authority
- JP
- Japan
- Prior art keywords
- input
- memory
- pins
- fixing
- response
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6097587U JPS63168700U (pt) | 1987-04-22 | 1987-04-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6097587U JPS63168700U (pt) | 1987-04-22 | 1987-04-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63168700U true JPS63168700U (pt) | 1988-11-02 |
Family
ID=30893882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6097587U Pending JPS63168700U (pt) | 1987-04-22 | 1987-04-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63168700U (pt) |
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1987
- 1987-04-22 JP JP6097587U patent/JPS63168700U/ja active Pending