JPS63167478A - Asymmetry correction circuit - Google Patents

Abstract

PURPOSE:To prevent the reproduction error of a synchronizing signal, etc., from being generated and to realize an optical system with resulting high reliability, by applying asymmetry correction automatically on the reproducing output of the synchronizing signal recorded in advance keeping a prescribed interval in a track direction. CONSTITUTION:A 1/2 frequency demultiplier 26 forms a bit lock with a very small amount of frequency fluctuation at every bit from a phase locked loop formed at a phase comparator 19, and referring pulse width formed from the bit lock is compared with the pulse width of an arranged output in which the synchronizing signal recorded in advance keeping the prescribed interval in a reproduced track direction is arranged at a binarization comparator 12 at a NAND gate 15 and a NOR gate 16, and the asymmetry error of a detected arranged output is fed back to the binarization comparator 12, and controls the slicing level of the binarization comparator 12, thereby, asymmetry can be corrected automatically.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an asymmetry correction circuit that corrects asymmetry in the reproduction output of an optical disc, and is applied to, for example, an optical disc system capable of recording and reproducing operations.

[Summary of the invention]

In an optical disc system capable of recording and reproducing operations, the present invention uses a phase-locked loop to generate a bit clock synchronized with an edge detection output of a synchronization signal obtained by detecting a synchronization signal recorded in advance at predetermined intervals in the track direction. A reference pulse of a predetermined width is formed using the bit clock, and the pulse width of the reference pulse and the pulse width of a shaped output obtained by shaping the regenerated synchronization signal by a waveform shaping circuit are sent to a comparison circuit. The asymmetry is corrected by controlling the slice level of the waveform shaping circuit using the comparison output of the comparison circuit. This system performs asymmetry correction to prevent errors in the reproduction of the synchronization signal due to variations in the output of the laser light used for reading information and dirt on the disc, making it possible to realize a highly reliable optical disc system. be.

[Conventional technology]

Conventionally, on optical discs, pit patterns recorded by digitizing audio signals, etc. are easily affected by output fluctuations of the laser light used for recording, development processing time, etc., and even when data is recorded with a duty of 50%, the optical In many cases, the duty of the playback output of the recorded pattern is not 50%.
Asymmetry correction is performed to correct the pulse of the reproduction output.

RFM (Eight to
Fourteen Modulation) In a so-called compact disk in which modulated digital data is recorded on an optical disk, when EFM-modulated digital data is integrated over a certain period of time, the probability of occurrence of logic "1" and rOJ is 50%. The asymmetry correction described above is performed by feeding back the deviation from the 50% value of the voltage obtained by integrating the EFM data as a slice level to a comparator that binarizes the reproduced RF signal.

In addition, since conventional compact discs are for playback only, a disc system has been proposed that uses a rewritable magneto-optical recording medium to ensure upward compatibility with the compact disc and allows data to be recorded. ing. For example, using a magneto-optical disk with a pre-group as a guide groove for tracking and 7-king, a potentiometer is provided on the recorder side to detect the radial position of the disk, and the disc is set at a constant linear velocity (CLV: Con5t).
A system has been proposed in which the CL* servo is performed so as to rotate with antLinear Velocity), and data is recorded using a crystal oscillator on the recorder side as a reference. This system requires an expensive potentiometer, and since the potentiometer has problems with reliability and longevity, the applicant has decided to
We have previously proposed a recording disk in which M-modulated frame synchronization signals and EFM-modulated absolute time information from the start to the end of the performance area are recorded in advance in a concave-convex pattern by so-called embossment. 61-240110
(see issue).

[Problem that the invention seeks to solve]

By the way, in a recording disk in which an EFM-modulated frame synchronization signal is recorded in advance in a concave-convex pattern by so-called embossing as described above, the concave-convex pattern portion of the frame synchronization signal etc. recorded in advance lasts for one frame time (13
6μsec), the time is only about 10μsec, and moreover, the logic “1” in the uneven pattern portion is
” and “0” are not necessarily 50%, so E
It is not possible to perform asymmetry correction using the deviation from the 50% value of the voltage obtained by integrating the FM data, and there is a risk that an error will occur when the reproduced RF signal is binarized.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, the present invention provides a highly reliable optical disk system by preventing the above-mentioned synchronization signal reproduction errors caused by fluctuations in the output of a laser beam for information reading, dirt on the disk, etc. The present invention aims to provide an asymmetry correction circuit with a new configuration that can automatically perform asymmetry correction on the playback output of synchronization signals recorded in advance at predetermined intervals in the track direction. be.

[Means for solving problems]

In order to solve the above-mentioned conventional problems, the asymmetry correction circuit according to the present invention is configured to synchronize with the edge detection output of the synchronization signal obtained by detecting the synchronization signal recorded in advance at predetermined intervals in the trunk direction. A bit clock is formed by a phase-locked loop, a reference pulse of a predetermined width is formed by the pit clock, and the pulse width of the reference pulse and the reproduced synchronization signal are shaped by a waveform shaping circuit to produce a shaped output pulse. The asymmetry is corrected by comparing the width with the width in a comparison circuit and controlling the slice level of the waveform shaping circuit using the comparison output of the comparison circuit.

[Effect]

In the asymmetry correction circuit according to the present invention, the frequency fluctuation per l bit of the bit clocker formed in a phase-locked loop so as to be synchronized with the edge detection output of the synchronization signal is extremely small, and the reference pulse formed from the bit clock is The asymmetry error of the shaped output is detected by comparing the pulse width of the reproduced synchronizing signal with the pulse width of the shaped output obtained by shaping the reproduced synchronization signal in the waveform shaping circuit. Therefore, asymmetry can be corrected by controlling the slice level of the waveform shaping circuit according to the asymmetry error.

〔Example〕

Hereinafter, one embodiment of the asymmetry correction circuit according to the present invention will be described in detail with reference to the drawings.

The embodiments shown in FIGS. 1 to 3 are those in which the present invention is applied to an optical disk system using the recording disk of Japanese Patent Application No. 61-240110 proposed earlier, and as shown in the schematic diagram of FIG. A pre-group 2 with a depth of λ/8 (λ is the wavelength of the laser beam) is formed in a spiral shape, and a concave-convex pattern formed by the bit 3 is formed along the circumferential direction on the land between the pre-groups 2. A magneto-optical disk 1 is used in which embossed areas 4 and data recording areas 5 on which magneto-optical recording is performed are arranged alternately at equal pitches.

The magneto-optical disk 1 has a recording format similar to that of a compact disk, and one frame is E.
F M (Eight to Four Tee
It consists of 588 channel bit data modulated (nModulation). The above one frame data consists of a 24-bit synchronization signal, a 14-bit (1 symbol) subcode, 14 x 32-bit (32 symbols) data such as performance information, parity, and 3-bit data between each symbol. consists of margin bits.

Among the data constituting one frame, the frame synchronization signal and subcode are recorded in advance in the embossed area 4 as a concave-convex pattern, and data such as performance information and parity are recorded as magneto-optical records in the data area 5. It is designed to let you do so. Here, the frame synchronization signal is an I
It is composed of an IT-IIT-2T uneven pattern.

Note that T is the channel bit clock (4.32MHz
> is the -period. Further, the above subcode is only for the Q channel and is absolute time information from the start to the end of the performance area.

In this embodiment, a reproduced RF signal (Sa) obtained from the magneto-optical disk 1 by an optical pickup head (not shown) is transmitted to the input terminal 11 of the signal processing circuit shown in FIG.
The signal is supplied to the binarization comparator 12 via. Here, a reproduced RF signal (Sa) having a waveform as shown in FIG. 2, which reproduces the frame synchronization signal and subcode recorded in the embossed area 3 of the magneto-optical disk 1, is transmitted to the signal input terminal of the signal processing circuit. 11.

In the first block diagram showing the configuration of the signal processing circuit of this embodiment, the binarization comparator 12 has a slice level (S L
), the reproduced RF signal (Sa) is sliced and binarized, and this binarized RF multiplied signal Sb) is sent to the edge detection circuit 14. It is supplied to the NAND gate 15 and the NOR gate 16 as well as to the data input terminal of the D-type flip-flop 17.

The edge detection circuit 14 is composed of a monostable multi-by-break that is triggered at the leading edge of the frame synchronization signal reproduced from the embossed area 3 of the magneto-optical disk l, and as shown in FIG. The first and second phase comparators 1 form an edge detection output (ED) that rises at every timing (to) of the leading edge of the signal.
It was supplied on 8.19.

The first phase comparator 18 compares the phases of the RF reference clock (RFck) with a frequency of 7.35 KHz supplied to the clock input terminal 20 and the rising edge of the edge detection output (ED), and performs the comparison. The output is supplied as a CLV servo signal to the spindle morph 22 via the phase compensation circuit 21.

In this embodiment, the second phase comparator 19 is a phase locked loop (PLL) for reproducing a bit clock (BT).
ρ), which forms a voltage-controlled oscillator (VCO) 2
The regenerated RF clock (CK) generated by the timing generator 23 based on the regenerated bit clock (BT) obtained by dividing the oscillation output by the oscillation output by the 172 frequency divider 26 and the edge detection output (E D ), and the comparison output is passed through the loop filter 14 to the voltage controlled oscillator (VCO) 25.
is supplied to the control input terminal of the The 1/2 frequency divider 26 is a voltage controlled oscillator (V) whose oscillation phase is fixed to the rising edge of the edge detection output (ED).
CO)25 frequency is 8°6'436 By dividing the oscillation output of MH2 by 1/2, the frequency is 4.32
Forming a 18MHz reproducing focus black vine (BT,),
This reproduced bit clock (BT) is supplied to the timing generator 23 and output from the clock output terminal 27. Furthermore, the above reproduced bit clock (BT)
is supplied to the clock input terminal of the above-mentioned flip-flop 17. Since the reproduced bit clock (BT) is phase-locked to the frame synchronization signal by comparing the phase with the rise resolution of the edge detection output (ED), the frequency fluctuation for each bit is extremely small. It will only change with a sufficiently long time constant.

The timing generator 23 is an R
M (Read 0nly Memory), and the above-mentioned regenerated bit clock (B
RF) and the first frame synchronization pattern signal (+1
17) and the second half of the frame synchronization signal
The frame synchronization pattern signal (-117) is read out. The first frame synchronization pattern signal (+117
) is supplied to the NAND gate 15, and the second frame synchronization pattern signal (-11T) is supplied to the NO
It is supplied to the R gate 16.

The NAND gate 15 and the NOR gate 16 output the frame synchronization signal portion of the binarized RF multiplied signal Sb) obtained by the binarization comparator 12 and each frame synchronization pattern signal (+117).

(-11T), the 7-symmetry error of the binarized RF multiplied signal Sb) is detected.

For example, when the pattern of the frame synchronization signal deviates from the normal asymmetry state shown by the solid line as shown by the dashed line or broken line in FIG. ) and the first frame synchronization pattern signal (+L
LT) and the first asymmetric error output (NA), or the frame synchronization signal portion of the binary RF multiplied signal Sb) by the NOR gate 16 and the second frame synchronization pattern signal (-11T). ) as the NOR output with the second asymmetry error output (No
) is obtained.

Then, the NAND gate 15 and the NOR gate 1
Each asymmetry error output (NA) obtained in 6,
(No) is an integrator 32 using operational amplifiers 30 and 31.
and a low-pass filter 33.
3 and is fed back to the binarization comparator 12. In this way, each of the above asymmetry error outputs (NA)
, (No) to the binarization comparator 12 via the loop filter 13, the slice level (SL) of the binarization comparator 12 becomes
Depending on the asymmetry error of the binarized RF multiplied signal Sb) obtained by the binarized comparator 12, it automatically changes as shown by the dashed line and dashed line in FIG. By feedback control of the slice level (SL) of the binarization comparator 12 using the asymmetry error outputs (NA) and (No), the binarized RF multiplied signal Sb) with the asymmetry error automatically corrected is It is obtained by the value comparator 12.

In this embodiment, the binarization comparator 12
The binary RF multiplied signal Sb) obtained in the above is outputted from the data output terminal 35 as reproduced data via the flip-flop 17 described above.

〔Effect of the invention〕

As is clear from the description of the embodiments described above, the asymmetry correction circuit according to the present invention uses a phase-locked loop to form a bit clock with extremely small frequency fluctuation for each bit, and uses a reference clock formed from this focused clock. The slice level of the waveform shaping circuit is determined according to the asymmetry error of the shaped output detected by comparing the pulse width of the synchronizing pulse and the pulse width of the shaped output obtained by shaping the reproduced synchronization signal in the waveform shaping circuit. By controlling this, asymmetry can be automatically corrected.

Therefore, by applying the present invention to an optical disc playback system, it is possible to prevent the above-mentioned synchronization signal playback errors due to fluctuations in the output of the laser beam for information reading, dirt on the disc, etc., and realize a highly reliable optical disc system. can do.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a signal processing circuit of a playback system of an optical disc system to which the present invention is applied.
FIG. 2 is a timing chart showing the operation of the above embodiment, and FIG. 3 is a schematic diagram showing the configuration of a magneto-optical disk used in the above embodiment. 1... Magneto-optical disk 4... Embossed area 5... Data recording area 11... Signal input terminal 12... Binarization comparator 13... Loop filter 14... Edge detection circuit 15. ...NAND gate 16...NOR gate 19...Phase comparator 23...Timing generator 25...Voltage controlled oscillator

Claims (1)

[Claims] A bit clock synchronized with the edge detection output of a synchronization signal obtained by detecting a synchronization signal recorded in advance at predetermined intervals in the track direction is formed in a phase-locked loop, A reference pulse of a predetermined width is formed, and a comparison circuit compares the pulse width of the reference pulse with the pulse width of a shaped output obtained by shaping the regenerated synchronization signal by a waveform shaping circuit, and the comparison circuit is compared. An asymmetry correction circuit that corrects asymmetry by controlling the slice level of the waveform shaping circuit at its output.