JPS63163647A - Virtual memory system - Google Patents

Abstract

PURPOSE:To improve the processing performance and the flexibility of a system, by incorporating an address conversion buffer in a processor having an address generating function, and providing a dynamic address conversion mechanism outside the processor. CONSTITUTION:The address conversion buffer TLB is separated from a DAT controller DATC in a memory managing device MMU, and the address conversion buffer TLB is incorporated in the processor, and also, the DAT controller DATC is set as a separate chip, then, it is provided outside the processor. The processor can perform a parallel processing based on a pipeline system by utilizing a built-in address conversion buffer TLB or mini-address conversion buffer MTLB, and it improves throughput while keeping the general purpose application of the processor, and also, it is possible to make the DAT controller DATC or the memory managing device MMU into a high function and a multilevel function, and the optimization of the system adopting a virtual memory system can be realized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a virtual memory system, and is applicable to, for example, a microcomputer system having a dynamic address translation mechanism (hereinafter referred to as a DAT controller). It is about effective techniques.

[Conventional technology]

Virtual storage is one way to overcome the constraints imposed by the physical properties of storage devices and create flexible program systems. A computer system using this virtual storage method is provided with an address conversion buffer 1 for converting a logical address output from a processing device into a physical address on a storage device within the bus cycle.

The address translation buffer is made to have the minimum necessary number of entries so that its hit rate is greater than or equal to a predetermined value. When the physical address corresponding to the logical address output from the processing unit is not stored in the address translation buffer, that is, when the address translation buffer misses, address translation is performed autonomously without any intervention from the control program (operating system). There is a DAT controller that performs paging processing for.

There is also a memory management device (memory management unit) that integrates an address translation buffer and a DAT controller.

Such a memory management device is described, for example, in Nikkei Electronics, published by Nikkei McGraw-Hill, December 5, 1983, pages 137 to 152.

[Problem that the invention seeks to solve]

FIG. 4 shows a storage system of a microcomputer system using a virtual storage method.

The memory management unit MMU has an address translation buffer TLB.
and a DAT controller (DATC), which converts the logical address output from the processing unit CPU into a physical address. The DAT controller includes an address translation buffer control circuit 'r L B C that controls access to the address translation buffer TL13.

The memory area of the main memory device MM is divided into pages of a predetermined size. The memory management unit MMU determines the upper focus point PA of the physical address by, for example, a so-called paging process in which a predetermined upper bit LAU of the logical address corresponds to a page address (frame number) on the physical address.
form a U. These page addresses are associated with the upper bits LAU of the logical address by a page translation table PTE provided in the main memory MM.

The DAT controller of the memory management unit MMU realizes paging processing by referring to this page translation table PTE, and stores the result in the address translation buffer TLB.
Store in.

Memory management unit MMU usually attempts address translation processing by first referring to address translation buffer TLB. As a result, if the physical address corresponding to the given logical address is stored in the address translation buffer TLB, that is, if the address translation buffer TLB is hit, the memory management unit MMU reads the physical address from the address translation buffer TLB. The physical address strobe signal PAS is output to the upper physical address bus PAU, and the physical address strobe signal PAS is sent to the main memory device MM. On the other hand, if the physical address corresponding to the logical address given to the address translation buffer TLB is not stored, that is, if the address translation buffer TLB misses, the DAT controller is activated and the page translation table PTE in the main memory device MM is Paging processing is performed.

By the way, when adopting a virtual storage method using a memory management unit MMU, there are two methods: one is to build the memory management unit MMU into the processing unit CPU, and the other is to treat the memory management unit MMU as one peripheral device and provide it outside the processing unit CPtJ. There is. However, research by the inventors of the present application has revealed that both methods have problems when considering the processing power and flexibility of the system. In other words, when the memory management unit MMU is built into the processing unit CPU, the bus cycle delay between when the address translation buffer hits and the physical address is output is eliminated and the system throughput is improved, but when the address translation buffer misses. When a hit occurs, the overhead for the processing unit CPU becomes large. In addition, by incorporating the memory management unit MMU, the versatility of the processing unit CPU is impaired, and the chip size of the processing unit CPU becomes large, which limits the area where the memory management unit MMU is formed. It becomes difficult to improve the functionality of the management device MMU.

On the other hand, when the memory management unit MMU is provided outside the processing unit CPU, the above problems caused by incorporating the memory management unit MMIJ are solved, but the bus cycle delay when the address translation buffer is hit is large. Become,
The throughput of the system is reduced.

An object of the present invention is to provide a virtual storage system that improves the processing power and flexibility of the system.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the first method is to separate the address translation buffer of the memory management device and the DAT controller, incorporate the address translation buffer into the processing device, and
The controller is a separate chip and installed outside the processing device. In the second method, a memory management device consisting of an address translation buffer and a DAT controller is provided independently outside the processing device, and the address translation buffer of the memory management device has fewer entries than the address translation buffer of the memory management device. The processing device has a built-in mini address translation buffer that stores part of the address translation information stored in the buffer redundantly.

[For production]

According to the above-mentioned means, the processing device can perform parallel processing using a pipeline method using the built-in address translation buffer or mini address translation buffer,
A system that can improve the throughput of the system while ensuring the versatility of the processing device, and can independently make the DAT controller or memory management device highly functional and multifunctional, and adopts the virtual memory 1 and 9 system. can be optimized.

[Embodiment 1] FIG. 1 shows a connection diagram of an embodiment of a microcomputer system used in a virtual storage system to which the present invention is applied.

In the computer system of this embodiment, the memory management unit MMU includes address translation buffers TLB, ! :D
Separated into ATD controller (DATC). Of these, the address translation buffer control circuit TLBC, which includes the address translation buffer TLB and the peripheral circuits of the address translation buffer TLB, is built into the processing device CPU, and is on the same chip (semiconductor substrate) as the processing device CPU main body, which includes the control unit CTL, etc. formed on top. The DAT controller is formed on a separate chip as an independent peripheral and is coupled to the processing unit CPU via a system bus.

The paging process in the computer system of this 1% example is a two-stage multi-paging method, although it is not particularly limited. The address signal output from the processing device CPU is divided into lower address signals AO to Ai and upper address signals Ai+L to Aj. this house,
The lower address signal AO-Ai is made into an offset section O8, and is sent directly to DAT via the lower address signal AL.
The data is transmitted to the controller and main memory device MM. on the other hand,
The upper logical address signal is first sent to the address translation buffer control circuit TLBC as internal logical address signals a i+ l to aj. Address translation buffer control circuit TLBC takes in internal logical address signals ai+1-, -33 in accordance with internal address strobe signal "T".

Although address translation Banff yTLB is not particularly limited,
It is composed of a plurality of content addressable memory elements, and stores a predetermined number of entries of the latest address translation results performed by the DAT controller, as will be described later. The address translation buffer 7a control circuit TLBC uses the index parts X1 and X2 sent as the internal logical address signal ai+1=aj as tags to convert the address translation buffer T
The upper physical address, that is, the frame number FN stored in the LB is associatively read out.

When the frame number FN corresponding to the internal logical address signal ai+1"aj is stored in the address translation buffer TLB, that is, when the address translation buffer TLB is hit, the frame number FN read from the address translation buffer "I' L I3 is the upper one. address signal A
It is assumed that i+1-Aj. On the other hand, internal logical address signal a
If the frame number FN corresponding to i+ 1 to aj is not stored in the address translation buffer TLB, that is, if the address translation buffer TLB misses, the internal logical address signal a i+ 1 to aj is directly transferred to the upper address signal Ai+1 to It is said to be Aj. Processing device CP
The operation of outputting the internal logical address signals a i+ 1 to aj from U to the address translation buffer control circuit TLBC is performed in parallel with other processing by the vibe line method, although there is no particular restriction. Therefore, the bus cycle delay of the physical address signal due to the address translation process of the address translation buffer TLB is eliminated, and the throughput of the system is improved.

The upper address signal Ai+1-Aj is sent to the DAT controller and the main memory device M via the upper address bus AU.
transmitted to M. Whether the upper address signals Ai+1 to Aj are logical addresses or physical addresses is determined by
Logical/physical address switching signal L sent from address translation buffer control circuit TLBG to DAT controller
/P. The DAT controller has the logical/physical address switching signal L/P negated. address translation buffer T in
It identifies that the LB has made a miss and starts paging processing. At this time, the paging processing execution signal PG is asserted (Here, regardless of the signal level, the signal is active or breathed is expressed as asserted. The same applies hereinafter)
do. Furthermore, the DAT controller
Halt signal HALT and bus error signal BE for
Assert RR. As a result, the processing unit CPU enters a halt state, releases the system bus, and uses the DAT controller as a bus mask.

As will be described later, the DAT controller uses the main storage device based on the offset signal O8 sent as the lower address signal AO−=Ai and the index parts X1 and The DAT controller refers to the page conversion table PTE in MM and obtains the frame number FN corresponding to the given index portions X1 and X2.When the paging process is completed, the DAT controller sends the halt signal HALT and the bus error signal BIF, RR is negated to release the bus, and the address translation buffer write signal TLBW is
is asserted, and the frame number FN and index portions X1 and X2 obtained by the address translation process are stored in the address translation buffer TLB. In this case, the entry number of the address translation bar TLB that stores the new address translation result is the entry designation signal E Ow E m
specified by. By negating the halt signal HALT and the bus error signal BERR, the processing unit CPU retries (re-executes) the interruption process related to the address conversion process.

As shown by the dotted line in FIG. 1, the processing unit cpU receives the address strobe signal AS and the upper address signal
1-Aj, but in this computer system, the address translation buffer control circuit TL
BC performs these functions.

Address signals transmitted via lower address bus AL and upper address bus AU are taken into the DAT controller and main memory device MM in accordance with address strobe signal AS. If the address translation buffer TLB misses, the DAT
Frame number FN is input from the controller to address translation buffer TLB. For this reason, the processing device CPU
The address translation buffer control circuit TLBC in
After a predetermined time has elapsed after asserting the address strobe signal AS, the upper address bus AU is brought into a high impedance state.

Data bus DT is coupled to processing unit CPU, DAT controller and main memory MM. This data bus D
At T, k+1-bit data DO-Dk is output from the processing device CPU, DAT controller, or main memory device MM in synchronization with a data transfer acknowledge signal DTAC. The moving direction of the data DO to Dk transmitted via the data bus DT is determined by the processing device CP.
It is determined by the read/write signal R/W sent from the U or DAT controller.

FIG. 2 shows a flowchart of address translation processing in the computer system of this embodiment. In the figure, the processing when the address translation buffer TLB is hit is shown by a solid line, and the processing when the address translation buffer TLB is hit is shown by a solid line.
The dotted line indicates the location where the LB mis-hits.

As shown in FIG. 2, the address conversion buffer LB provided in the processing unit CPU is constituted by an associative memory consisting of a plurality of entries, and includes XM address signal index sections XI and X2 and these indexes. The upper physical address corresponding to the frame, that is, the frame number FN is stored. Address translation buffer T L
B is updated whenever the DAT controller completes paging processing. Therefore, the frame number of the recently accessed physical address and the index part of the corresponding logical address are always stored in the address translation buffer TLB for a predetermined number of entries. Further, the number of entries in the address translation buffer TLB is set so that its high +- rate is, for example, 95% or more. Therefore, most of the normal address translation processing in this computer system is completed by simply referring to the address translation buffer TLB in the processing unit CPU.

The address translation buffer control circuit TLBC sets the internal logical address signal ai+1=aj (A-supplied index parts X1 and X2 as read tags of the address translation buffer TLB.Address translation buffer 'I'
LB is the given tag, that is, the index part Xl
and X2 and the index parts stored in all entries are instantly compared. If there is an entry whose index parts match, the address translation buffer T L
B7> (If hit, the address translation buffer control circuit TLBC reads the frame number FN of the entry and outputs it on the upper address bus AU as the upper address signal Ai+ 1 = A j. The lower address signals AO to Ai
That is, these address signals AO-Aj, to which offset signal O5 is output as is, are taken into main memory device MM in accordance with address strobe signal AS simultaneously asserted by address translation buffer control circuit TLBC. At this time, the logical/physical address switching signal L/P for the DAT controller is asserted by the address translation buffer control circuit TLBC, so the DAT controller does not perform paging processing.

On the other hand, if there is no entry in the address translation buffer TLB in which both index parts X1 and X2 match, that is, if there is a miss in the address translation buffer TLB, the address translation pants 1 control circuit TLBC
outputs the internal logical address signals a i+1 to aj as they are as upper address signals Ai+1 to Aj, and asserts the address strobe signal π. Also, logic/
The physical address switching signal L/T is negated to inform the DAT controller that the upper address signal Ai+1=Aj is a logical address signal. As a result, D
The AT controller starts paging processing to refer to the page translation table PTE in the main memory MM.

As described above, the paging process in the DAT controller of this embodiment employs a two-stage multi-paging method. Therefore, as shown in FIG. 2, the page conversion table PTE in the Q device MM, which is mainly described, is composed of two sets of conversion tables PTEI and PTE2 provided corresponding to the index sections X1 and X2. Among these, the first conversion table PTE1 is stored in the main storage M
They are arranged with a predetermined address P1 of M as the first address. The conversion table PTE1 stores a block number BN for address modification of the stupid conversion table PTE2 such as control bits for memory protection.The address of the conversion table device that is actually accessed is a logical address. Modified by the first index part X1 of the signal, it becomes P l +
Multiple blocks are placed with this as the starting address. The conversion table PTE2 stores a frame number FN used as an upper physical address in addition to a control focus for memory protection. The block start address of the conversion table PTE2 is modified by the block number BN read from the conversion table PTE1, and
2 +BN. Furthermore, the address within the block that is actually accessed is determined by the second of the logical address signals.
Repaired by index section X2, P2+BN
+X2.

The DAT controller accesses the page translation table PTE of the main memory device MM twice while performing address calculations and the like to access the translation tables PTEl and PTE2, thereby forming a physical address signal. In other words, D.A.
The T controller finally converts the second conversion table PTE2
The frame number FN read from is used as the upper physical address signal. This upper physical address signal, that is, the frame number FN and the index portions X1 and X2 of the given logical address signal are stored in an address translation buffer TLB provided in the processing device CPU. These physical address signals are read from the address translation buffer TLB during a retry of the processing unit CPU after the paging process of the DA′r controller is completed, and are sent to the main memory unit MM via the upper address bus AU.
sent to.

As described above, in the computer system of this embodiment, the memory management unit MMU uses the address translation buffer TLB.
and DAT controller. Of these, address translation buffer TLB and address translation buffer TLB
Address translation buffer control circuit TLB including peripheral circuits of
C is built in the processing device CPU, and the DAT controller is formed on an independent chip as a peripheral device of the processing device CPU. Since the processing device CPU can refer to the built-in address translation buffer TLB through parallel processing using a pipeline system, bus cycle delays associated with address translation processing are eliminated.

Further, since the DAT controller is formed on an independent chip, it can be made highly functional and multifunctional without hindering the versatility of the processing unit cPU. Thereby, the throughput of the computer system can be improved and the flexibility of the system can be ensured.

[Embodiment 2] FIG. 3 shows a connection diagram of another embodiment of a computer system used in a virtual storage system to which the present invention is applied. In the following explanation, parts that are not particularly explained are the same as those of the computer system of the first embodiment.

In the computer system of this embodiment, a memory management unit MMU consisting of an address translation buffer TLB and a DAT controller (including an address translation buffer control circuit TLBC) is provided independently outside the processing unit CPU. This memory management unit MMU is connected to the processing unit CP.
It is formed on a separate chip from U. The processing unit CPU has fewer entries than the address translation buffer TLB, and the address translation buffer T
A mini address translation buffer MTLB that redundantly stores a part of the address translation information stored in LB, and a mini address translation buffer control circuit MTLBC including a peripheral circuit of the mini address translation buffer MTLB are provided. These mini address translation buffer and mini address translation buffer control circuit MTLBC are formed on the same chip together with the main body of the processing device CPU.

The mini address translation buffer MTLB has a relatively small number of entries (
For example, 4 entries).

The processing unit CPU refers to the mini-address translation buffer MTLB through parallel processing based on the vibe line method, and converts a logical address into a physical address at high speed. Mini address translation buffer M T L B When a mistake hits,
Address translation processing is performed by the address translation buffer TLB of the memory management unit MMU. Memory management device MM
U's address translation buffer TLB is configured to have a relatively large number of entries such that its hit rate is, for example, 95% or more. When the address translation buffer TLB hits, a predetermined physical address signal is output to the address bus, and a mini address translation buffer write signal MTLBW is asserted to the mini address translation buffer control circuit MTLBC, and the bus cycle Mini address translation buffer M T
1. T't switching of B is performed. As a result, bus cycle extension of the processing unit cI'U is eliminated within the range of the hit rate of the mini-address translation buffer MTLB, and the throughput as a combinator system is improved.

In FIG. 3, the mini-address translation buffer MTLB is supplied with upper internal logical address signals a i+ 1 to aj via the internal address bus of the processing unit CPU. These internal logical address signals a i+ 1 to aj
includes index portions Xi and X2, and is taken into the mini address translation buffer control circuit MTLBC according to the internal address strobe signal aS that is asserted at the same time.

As mentioned above, the mini address translation buffer MTLB is
It has a relatively small number of entries and is composed of a plurality of associative memory elements. The mini address translation buffer MTLB stores the same address translation information as the address translation buffer TLB of the memory management unit MMU, that is, index parts X1, X2 and frame numbers FN corresponding to the index parts, as many as the number of entries.

The mini address translation buffer control circuit MTLBC receives an upper internal logical address signal a sent from the processing unit CPU.
The mini address translation buffer MTLB is read associatively using i+1"aj, that is, the index parts X1 and X2 as tags. If the mini address translation buffer MTLB is hit, the mini address translation barrage control circuit MTL is read.
BC from its entry to index parts XI and X
The frame number FN corresponding to 2 is read out and sent to the upper address bus AU as upper physical address signals Ai+1 to Aj. At this time, the mini address translation buffer control circuit MTLBC asserts the physical address strobe signal PAS and also asserts the logical/physical address switching signal L/7 to
Notify the MU that the address signal on the upper address bus AU is a physical address signal. As a result, the memory management device MMU is not activated, and the physical address signal output from the mini address translation buffer control circuit MTLBC is directly transmitted to the main memory device MM.

On the other hand, if the mini address translation buffer MTLB misses the internal logical address signal ai+1=aj supplied from the processing unit CPU, the mini address translation buffer control circuit MTLBC is in a state where the logical/physical address switching signal L/P is negated. The address strobe signal τ is asserted to notify the memory management unit MMU that the mini address translation buffer MTLB has mishit. At this time, the internal logical address signals a i+ 1 to aj are directly transmitted to the upper address bus AU as the upper logical address signals Ai+1-Aj.

The memory management unit MMU receives an address strobe signal AS.
Since the logical/physical address switching signal L/P is negated when is asserted, it is identified that the mini address translation buffer MTLB has mishit, and address translation processing is started. That is, the DAT controller uses the index sections X1 and X2 supplied as the upper logical address signal Ai+1''Aj as tags, and associatively reads the address translation buffer TLB.

If the address translation buffer TLB goes high, DA
The T controller reads the frame number FN from the address translation buffer TLB and sends it onto the upper address bus AU as upper physical address signals Ai+I to Aj. At this time, the DAT controller asserts the physical address strobe signal PAS and also asserts the mini address translation buffer write signal MTLBW.

The mini-address translation buffer control channel MTLBC in the processing unit C-P U operates before the physical address is output from the memory management unit MMU, that is, after the logical address signal is fetched into the memory management unit MMU by the address strobe signal As. , puts the upper address bus AU into a high impedance state. In addition, the memory management unit MMU outputs the mini address translation buffer write signal M T L
When BW is asserted, the upper address bus AU
Frame number FN transmitted above and lower address bus A
The index portions XI and X2 transmitted on L are taken in and written to the mini address translation buffer MTLB. Although not particularly limited, the mini address translation buffer M T
Selection of entries when rewriting LB is performed simply in the order of entry numbers without using any special algorithm.

The main memory device MM operates according to the physical address strobe signal PAS asserted by the mini address translation buffer control circuit MTLBC or the memory management device MMU.
Take in the physical address signals on the upper address bus AU and lower address bus AL. Also, according to the read/write signal R/W, write data on the data bus DT is taken in, or devised data is sent to the data bus DT.
Send to. The main memory device MM transmits a data transfer confirmation signal D T at the time when a write operation or a read operation is completed.
Assert A C, K.

FIG. 4 shows a flowchart of an embodiment of address translation processing in the computer system of this embodiment. In the figure, a solid line indicates the processing when the mini address translation buffer MTLB in the processing unit CPU has a hit, and the mini address translation buffers MTL, B have a miss and the address translation buffer TLB of the memory management unit MMU has a hit. The dotted line indicates the processing when this occurs.

Further, the process when both the mini address translation buffer MTLB and the address translation buffer TLB have a miss is shown by a chain line. Memory management device M
The paging process performed when there is a miss in the address translation buffer TLB of the MU is the same as in the flow diagram of FIG. 2, and is omitted.

In FIG. 4, the mini address translation buffer MTLB provided in the processing device CPU is not particularly limited, but
A logical address signal LA configured by an associative memory consisting of four entries and output from the processing unit CPU.
The index portions X1 and X2 of , and the upper physical address, that is, the frame number FN corresponding to these index portions are stored. The mini address translation buffer MTLB is the address translation buffer TL of the memory management unit MMU when the mini address translation buffer MTLB has a miss.
When B is hit, the mini address translation buffer write signal MTLBW is asserted by the memory management unit MMU, so that the data can be rewritten at any time. therefore,
The mini address translation buffer MTLB always stores four entries of the frame number of the recently accessed physical address and the index part of the corresponding logical address. Also, this mini address translation buffer IM
By having four entries, 'I'LB is made to have a hit rate greater than a predetermined value.

For this reason, the normal address translation process in this computer system is a mini address translation bar.

Within the hit rate of Fa M ``1' LB,
Mini address translation buffer M T in the processing unit CPU
The process ends by simply referencing the LB.

The mini address translation buffer control circuit MTLBC uses the index sections x1 and x2 supplied as the internal logic AT1/S signals ai+1 to aj as read tags for the mini address translation buffer MTLB. The mini address translation buffer MTLB converts the given tag, i.e.
Instantly compare and match the system parts X1 and X2 with the inte-nox parts stored in all entries. If there is an entry in which both index sections fail, that is, if 4TI, B hits the mini address translation buffer, the mini address translation buffer control circuit MTLBC reads the frame number FN of that entry and uses the upper physical address signals Ai+1 to It is output as Aj onto the upper address bus AU. Furthermore, the lower address signal AO=Ai, that is, the offset signal O8, is output as is to the lower address bus AL. These address signals AO to Aj are connected to the eJ physical address strobe signal PA which is simultaneously asserted by the mini address translation buffer control circuit MTLBC.
According to S, the data is taken into the main memory device MM. At this time, the mini address translation buffer control circuit MTLI3C provides logic/? for the memory management device MMU. In order to assert the address switching signal L/P, the memory management unit MMU does not perform any address conversion processing.

On the other hand, the mini address translation buffer M in the processing unit CPU
If there is no entry in TLB in which both index parts X1 and x2 match, that is, if there is a miss in the mini address translation buffer MTLB,
The mini address translation buffer control circuit MTLBC outputs the internal logical address signals ai+1 to aj as they are as upper address signals Ai+1 to Aj, and asserts the address strobe signal AS. It also negates the logical/physical address switching signal L/P and notifies the memory tube ff device MMU that the upper address signals Ai+1 to Aj are logical address signals. Thereby, the memory management device MMU starts address translation processing.

As described above, the address translation buffer TLB of the memory management unit MMU is configured by a plurality of content addressable memory elements, and has the number of entries such that the hit rate thereof is, for example, 95% or more.

Each entry has the mini address translation buffer M
Similar to TL B, the frame number FN of the recently accessed physical address and the corresponding index section
1 and X2 are stored. DA of memory management unit MMU
First, the T controller uses the index parts X1 and X2, which are transmitted as upper logical address signals via the upper address bus AU, as tags to convert the address translation buffer T.
Performs associative reading of LB.

If there is an entry in the address translation buffer TLB with matching index parts X1 and The address is sent to the upper address bus AU as follows. At this time, the physical address strobe signal PAS for the main memory device MM is asserted, and the mini address translation buffer write signal MTLBW for the mini address translation buffer control circuit MTLBC is asserted.

The mini address translation buffer control circuit MTLBC takes in the upper physical address signal, that is, the frame number FN, transmitted via the upper address bus AU when the mini address translation buffer write signal MTLBW is asserted, and also receives the frame number FN during the bus cycle. The mini-address conversion control circuit MTLBC that takes in the lower logical address signals, that is, the index portions X1 and X2 transmitted via the lower address bus AL, converts the mini-address conversion buffer MTLB specified by the built-in pointer. These frame numbers FN and index parts X1 and X2 are written in the entry. Furthermore, when the physical address strobe signal PAS is asserted, the main memory device MM takes in the physical address signal transmitted via the upper address bus AtJ and the lower address bus AL, and according to the read/write signal R/W. The specified write or read operation is started.

On the other hand, if there is no entry in the address translation buffer 'l' LB with matching index parts X1 and X2, that is, if there is a miss in the address translation buffer TLB, the memory management unit MMU
Paging processing using the page conversion table PTE in liMM is started. At this time, the memory management unit MMU sends a halt signal 14 A L to the processing unit (Yoshi CPU).
'i' and bus error signal BERR are asserted;
- Puts the processing device CPU into a halt state and becomes a bus mask.

Thereafter, after performing the same paging process as in Example 1 of FIG. 2, the resulting frame number FN and the corresponding index parts X1 and X2 are written into a predetermined entry of the address translation buffer TLB, The halt signal HALT and bus error signal BERR for the processing unit CPU are negated. As a result, the processing device CPU retries the interruption process related to address translation. In this retried bus cycle, the process for the case where the address i translation buffer TLB hits is executed, and the frame number FN written in the address translation buffer TLB is read out again as an upper physical address signal. Furthermore, in this retried bus cycle, the mini address translation buffer M T LB in the processing unit CPU is rewritten.

As described above, in the combinator system of this embodiment, the memory management unit MMU consisting of the address translation buffers TLB and DA controller is provided independently outside the processing unit CPU, and the address translation buffer TL
A mini-address translation buffer MTI, B that has a smaller number of entries than B and redundantly stores a part of the address translation information stored in the address translation buffer TLB.
is provided within the processing device Ck'U. Processing device CP t
J refers to the mini-address translation buffer MTLB by parallel processing using a pipeline method, and converts a logical address into a physical address at high speed. When the mini address translation buffer MTLB misses, the memory management device M
Address translation processing by the address translation buffer 'rLB of the MU is started. Here, when the 'yfi address translation buffer TLP is hit, a predetermined physical address signal is sent to the main memory device MM, and within that bus cycle, the mini address translation buffer MTL is
B is rewritten. As a result, the bus cycle delay of the processing unit CPU is eliminated within the range of the hit rate of the mini address translation buffer MTLB, and the throughput of the computer system is improved. Also,
The processing unit CPU only needs to have a built-in mini address translation buffer MTLB, which has a small number of entries, so its versatility is not hindered, and if a virtual memory method is not adopted, the mini address translation buffer MTLB can be used for other purposes. It can also be used as a storage device. moreover,
Needless to say, since the memory management unit 3MMu is formed on an independent chip, it is possible to increase the functionality and use multiple machines without worrying about the layout of the processing unit cPU.

As shown in the above two embodiments, when this invention is applied to a convenience store system using a virtual storage method, the following effects can be obtained. That is, (1) Address translation buffer and DAT of memory management device
By separating the controller and incorporating the address translation buffer into the processing device, and by providing the DAT controller as a separate chip and external to the processing Vl, the processing device can perform parallel processing using a pipeline method, and the address translation buffer The effect is that bus cycle delays associated with address conversion can be eliminated within a hit rate range of 1.

(2) A memory management device consisting of an address translation buffer and a DAT controller is provided independently outside the processing device, and the number of entries stored in the address translation buffer of the memory management device is smaller than that of the address translation buffer of the memory management device. By incorporating a mini-address translation buffer into the processing unit that stores part of the address translation information redundantly, the processing unit can perform parallel processing using the pi-bry:/ method, which reduces the hit rate of the mini-address translation buffer. The effect is that bus cycle delay associated with address conversion can be eliminated within the range.

(3) According to the above item (2), when the virtual storage method is not adopted, the processing device can be used as an associative storage device for other purposes such as the mini address translation buffer 4.

(4) Items (1) to (2> above) ensure the versatility of the processing device, improve the throughput as a combinator system, and independently improve the functionality of the DAT controller or memory management device. This has the advantage of being multi-functional and optimizing a system that uses a virtual memory method.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it is possible to make various changes without further advancing the gist of the invention. Not even. For example, the processing device does not need to perform address translation processing using an address translation buffer or an address translation buffer using a per-f line method, and
The memory management device including the controller may be formed on one chip along with other peripheral devices. Furthermore, the paging process performed by the Dl to T controllers may employ a multilevel paging method with three or more stages, or may use a segment method or a combination of a segment method and a paging method. The try processing when the address translation buffer has a mishit does not have to be based on the halt signal HALT and the bus error signal "ERR," and combinations of other signal lines are not particularly limited by this embodiment. Furthermore, various embodiments such as specific configurations of computer systems and memory configurations can be explored.

In the above explanation, the invention made by the present inventor was mainly applied to a computer system that adopts a virtual memory method, which is the field in which the invention became famous, but the present invention is not limited to this (for example, The present invention, which is applicable to other control systems and data processing systems, is widely applicable to digital systems using a virtual 200 million system.

〔Effect of the invention〕

A simple explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, the address translation buffer of the memory management device and the DAT controller can be separated, the address translation buffer built into the processing device, and the DAT controller made into a separate chip and provided outside the processing device, or the address translation buffer and the DAT controller can be separated. J) A memory management device consisting of an AT controller is provided outside the processing device, and has a smaller number of entries than the address translation buffer of the memory management device, and a part of the address translation information stored in the address translation buffer of the memory management device is By incorporating the mini-address translation buffer 1 that stores redundantly into the processing device, the processing device can perform parallel processing using the pipeline method, and the throughput can be improved while ensuring the versatility of the processing device. At the same time, L) the AT controller can be independently made highly functional and multi-functional, and a system employing a virtual memory method can have an optimal configuration.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing an embodiment of a computer system used in a virtual storage system to which the present invention is applied. FIG. 2 is a connection diagram showing an embodiment of the address conversion process of the computer system of FIG. 1. Flowchart, FIG. 3 is a connection diagram showing another embodiment of a computer system used in a virtual storage system to which the present invention is applied, and FIG. FIG. 5, a flowchart showing an embodiment, is a connection diagram showing an example of a conventional combinator system. TLB...Address translation buffer, TLBC...Address translation buffer control circuit, MTLB...Mini address translation buffer, MTLBC...Mini address translation t isofa control circuit, DATC...DAT controller, M M tJ・・Memory management device, CPU...
Central processing unit, MM... main memory, PTE... page conversion table. LA...Logical address, PA...Physical address, P
TEL, PTE2...Page conversion table. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Scope of Claims] 1. A virtual storage system characterized in that an address translation buffer is built into a processing device having an address generation function, and a dynamic address translation mechanism is provided outside the processing device. 2. A memory management device including a first address translation buffer and a dynamic address translation mechanism is provided outside a processing device having an address generation function, and has fewer entries than the first address translation buffer and has a memory management device including a dynamic address translation mechanism. A virtual storage system characterized in that the processing device includes a second address translation buffer that redundantly stores a part of the address translation information stored in the translation buffer. 3. The second address translation buffer stores the first address when the second address translation buffer misses and the first address translation buffer hits a given logical address. 3. The virtual storage system according to claim 2, wherein the physical address output from the translation buffer and the address translation information related to the physical address are written within the same bus cycle.