JPS63163069U - - Google Patents

Info

Publication number
JPS63163069U
JPS63163069U JP5423787U JP5423787U JPS63163069U JP S63163069 U JPS63163069 U JP S63163069U JP 5423787 U JP5423787 U JP 5423787U JP 5423787 U JP5423787 U JP 5423787U JP S63163069 U JPS63163069 U JP S63163069U
Authority
JP
Japan
Prior art keywords
level
video signal
composite video
input
sync chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5423787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5423787U priority Critical patent/JPS63163069U/ja
Publication of JPS63163069U publication Critical patent/JPS63163069U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例によるノイズキヤン
セル回路の構成を示す図、第2図は同実施例の動
作を説明するためのタイミングチヤート、第3図
は従来のノイズキヤンセル回路の構成を示す図、
第4図は第3図の動作を説明するためのタイミン
グチヤートである。 11…ビデオ入力端子、12…クランプ回路、
13,14…カレントミラー回路、15…コンパ
レータ、16,17…オペアンプ、18…ビデオ
出力端子。
FIG. 1 is a diagram showing the configuration of a noise canceling circuit according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the same embodiment, and FIG. 3 is a diagram showing the configuration of a conventional noise canceling circuit. figure,
FIG. 4 is a timing chart for explaining the operation of FIG. 3. 11...Video input terminal, 12...Clamp circuit,
13, 14... Current mirror circuit, 15... Comparator, 16, 17... Operational amplifier, 18... Video output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力される複合映像信号のシンク・チツプ・レ
ベルをクランプする手段と、上記シンク・チツプ
・レベルに対して予め設定されたレベル差以上の
入力がなされたことを検出する手段と、この手段
から検出信号が出力されている期間上記複合映像
信号を一定レベルに置換する手段とを具備したこ
とを特徴とするノイズキヤンセル回路。
means for clamping the sync chip level of the input composite video signal; means for detecting that an input is greater than a preset level difference with respect to the sync chip level; and detection from the means. A noise canceling circuit comprising means for replacing the composite video signal with a constant level while the signal is being output.
JP5423787U 1987-04-10 1987-04-10 Pending JPS63163069U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5423787U JPS63163069U (en) 1987-04-10 1987-04-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5423787U JPS63163069U (en) 1987-04-10 1987-04-10

Publications (1)

Publication Number Publication Date
JPS63163069U true JPS63163069U (en) 1988-10-25

Family

ID=30881042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5423787U Pending JPS63163069U (en) 1987-04-10 1987-04-10

Country Status (1)

Country Link
JP (1) JPS63163069U (en)

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