JPS63163041U - - Google Patents

Info

Publication number
JPS63163041U
JPS63163041U JP1987053396U JP5339687U JPS63163041U JP S63163041 U JPS63163041 U JP S63163041U JP 1987053396 U JP1987053396 U JP 1987053396U JP 5339687 U JP5339687 U JP 5339687U JP S63163041 U JPS63163041 U JP S63163041U
Authority
JP
Japan
Prior art keywords
circuit
clock signal
level
disconnection
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987053396U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987053396U priority Critical patent/JPS63163041U/ja
Publication of JPS63163041U publication Critical patent/JPS63163041U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Maintenance And Management Of Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP1987053396U 1987-04-10 1987-04-10 Pending JPS63163041U (enrdf_load_stackoverflow)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987053396U JPS63163041U (enrdf_load_stackoverflow) 1987-04-10 1987-04-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987053396U JPS63163041U (enrdf_load_stackoverflow) 1987-04-10 1987-04-10

Publications (1)

Publication Number Publication Date
JPS63163041U true JPS63163041U (enrdf_load_stackoverflow) 1988-10-25

Family

ID=30879423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987053396U Pending JPS63163041U (enrdf_load_stackoverflow) 1987-04-10 1987-04-10

Country Status (1)

Country Link
JP (1) JPS63163041U (enrdf_load_stackoverflow)

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