JPS63157674U - - Google Patents
Info
- Publication number
- JPS63157674U JPS63157674U JP1987050446U JP5044687U JPS63157674U JP S63157674 U JPS63157674 U JP S63157674U JP 1987050446 U JP1987050446 U JP 1987050446U JP 5044687 U JP5044687 U JP 5044687U JP S63157674 U JPS63157674 U JP S63157674U
- Authority
- JP
- Japan
- Prior art keywords
- board
- pin
- checker
- correction
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987050446U JPS63157674U (en:Method) | 1987-04-01 | 1987-04-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987050446U JPS63157674U (en:Method) | 1987-04-01 | 1987-04-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63157674U true JPS63157674U (en:Method) | 1988-10-17 |
Family
ID=30873816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987050446U Pending JPS63157674U (en:Method) | 1987-04-01 | 1987-04-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63157674U (en:Method) |
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1987
- 1987-04-01 JP JP1987050446U patent/JPS63157674U/ja active Pending