JPS63156260A - Virtual storage controller for image data - Google Patents

Abstract

PURPOSE:To shorten a loss time and to realize efficient use by dividing an image equally into plural blocks according to its attribute, and specifying the position and size of a block in the original image and rolling in and out the image in block units. CONSTITUTION:The image data 9 in an actual storage device 3 is divided into plural blocks according to its attribute and rolled out in a virtual storage device 4. For the purpose, an address control circuit 1 specifies block size by a block size specifying means 10 to divide the image 9 equally, and specifies the position address of a block. An image data address arithmetic means 13 inputs in-block address specification information successively by block position addresses, converts it into an image data address specifying a picture element in an image data buffer 2, and outputs it to a buffer 1. Then image data of a necessary block is rolled in from the device 4. Thus, only a necessary block is rolled in and out to shorten the loss time and improve the use efficiency.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a virtual storage control device that performs virtual storage control of image data between a real storage device and a virtual storage device. A means of equally dividing into multiple rectangular or square blocks and accessing them in block units according to known embryonic characteristics, especially a method of arbitrarily changing the block position on image data that is input/output between a real storage device and a virtual storage device. By having the means to set
Virtual storage of image data that enables virtual storage control for only necessary blocks, reduces time loss during roll-in/roll-out, and enables efficient use of virtual storage 1. I! It is a control device.

[Industrial application field]

The present invention relates to a virtual storage device that can efficiently control virtual storage of image data.

[Conventional technology]

When performing computer image processing, image information requires 1 bit to several bits for each pixel, and in order to perform processing with a high 1W image resolution, for example, 256 x 25 bits per image is required.
It requires a large number of pixels, such as 6 pixels. For this reason, image processing requires a large amount of memory, and conventionally, D
IC memory such as RAM (dynamic RAM) is used.

[Problem that the invention seeks to solve]

However, as processing becomes more complex, the capacity of DR becomes larger and larger.
AM has been required, and this has created a problem in that it conflicts with the demand for miniaturization of the device.

In order to solve the above problem, it is possible to use the concept of virtual letters f and α. Conventional virtual storage devices are for general programs, and since such programs do not have very large amounts of data and are not required to have high processing speed, the data is stored during the program execution time. can be rolled in from the virtual storage device to the real memory, or rolled out from the real memory to the virtual storage device, making it possible to make the time loss due to roll-in/roll-out invisible to the user.

However, when a large amount of image data is applied to such a virtual storage device, time loss due to roll-in/roll-out becomes visible to the user because the amount of data is enormous. In addition, since image data is often calculated for each pixel and displayed immediately, the time loss due to roll-in/roll-out adds a large 16 ME to the calculation speed and display speed. It had some problems.

In order to solve the above problems, the present invention divides one image equally into a plurality of blocks according to its responsiveness, and performs virtual memory control for each block, thereby reducing time loss due to roll-in/roll-out. It is an object of the present invention to provide a virtual storage control device for image data that enables efficient use of a virtual storage device.

[Means for solving problems]

In order to solve the above problems, the present invention has a basic configuration shown in FIG. 1. An image data buffer 2 is arranged between the real storage device 3 and the virtual storage device 4 via a data bus 7.8, a multiplexer 5, and a divider 6. Image data 9 for one sheet is temporarily stored in the buffer. Address control for the image data 9 in the image data buffer 2 is controlled by the image data address 18 from the address control means 1.

The address control circuit 1 includes block size specifying means 10.
, a block position addressing means 11 which inputs the block size 14.15 from said means, and an intra-block addressing means 12 which is an address counter, and further a block position address 16 and an intra-block address 17 from said means and said block. The image data address calculation means 13 inputs the size 14.15 and outputs the image data address 18.

[For production]

In the configuration shown in FIG. 1, first, one sheet of image data 9 is temporarily stored from the real storage device 3 into the image data buffer 2 via the data bus 7 and the multiplexer 5. Next, this image data 9 is equally divided into a plurality of rectangular or square blocks according to the characteristics of both images, such as ``vertical stripes'' and ``the rope clusters are arranged in an orderly manner.'' Divider 6, data bus 8 for each bus
The data is rolled out to the virtual storage device 4 via.

For this purpose, in the address control circuit 1, the user first specifies the block size in the horizontal direction (X
direction) and vertical direction (X direction) block size 14.1
Specify 5.6 Next, when the image data 9 is equally divided into blocks of this size, the position address in the image data of each block is determined by the block position address designating means 11 in block units, for example, in order of the smallest number, block 0. , block 1, block 2, and so on. On the other hand, in the intra-block addressing means 12, each i! The addresses of iii are sequentially specified with the beginning of each block being address 0. This operation is performed by incrementing addresses for the number of pixels determined from the block size 14.15 using an address counter. For each address 16, the intra-block address specification means 17 from the intra-block address specification means 12 is sequentially input, and the image data address specifies each pixel in each corresponding program 7 of the image data 9 in the image data buffer 2. 18 and output to the image data buffer 2.

By the above operation, one full-out of one image data 9 to the virtual storage device 4 is performed, for example, block O, block 1, .
This is done on a block-by-block basis. On the other hand, when a process is started that only requires calculation of a part of the image data 9, that is, a specific block, only the corresponding block is transferred from the virtual storage device 4 via the data bus 8 and the multiplexer 5. and rolls into image data buffer 2. At this time, the block is inserted into the original image by controlling the address in exactly the same way as in the rollout case, and the divider 6, data bus 7
The data is transferred to the real storage device 3 via.

With the above operation, when it is necessary to perform calculations on only a part of a large image, it is sufficient to roll in only the necessary blocks, and the virtual memory f, α1 DIJ 711 can be performed at a high rate. It becomes possible.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail.

(Configuration of image data address calculation means (Figure 2)) First, the basic configuration of the image data virtual storage control device according to the present invention is as shown in Figure 1, and since the configuration has been described above, it will be omitted. do. Next, FIG. 2 is a diagram showing the configuration of a specific embodiment of the image data address calculation means 13 of FIG. 1. Block position addressing means 11 in FIG.
The block position address 16 from is input to the block start address calculation circuit 19, and here the X direction block start address 24 and the X direction block start address 25 are input.
are calculated, and each X-direction image data address calculation circuit 2
1, and is output to the X-direction image data address calculation circuit 22. On the other hand, the intra-block addressing means 1 in FIG.
The intra-block address 17 from 2 is input to an intra-block address separation circuit 20, where the intra-block address 17 is separated into an X-direction intra-block address 26 and a y-direction intra-block address 27, each of which is an X-direction image data address. It is output to the arithmetic circuit 21 and the X-direction image data address arithmetic circuit 22. In the xl and X direction image data address calculation circuits 21 and 22,
A direction image data address 28 and an X direction image data address 29 are calculated and both are input to the image data address synthesis circuit 23. Here, the X and X direction image data addresses 28 and 29 are combined into one image data address 18 and output to the image data buffer 2 in FIG.

(Operation of image data virtual storage control device (Figs. 3 to 1)
(Fig. 1)) Next, the operation of the embodiment shown in Figs. 1 and 2 will be explained. FIG. 3 shows the principle of transferring image data on the real storage device 3 (FIG. 1) to the virtual storage device 4. In FIG. 3, one piece of image data 9 on the real storage device W13 is composed of 2 bar pixels (in the X direction)×29
Pixel (X direction) (M.

It is assumed that the number of pixels is (N is an integer greater than or equal to 0), and addresses are assigned in binary numbers to each pixel in order from 0 in the direction of arrow 24, with the upper left of the image as the origin O. This is defined as image data address 18, and is shown in Fig. 5 (f1).
It is expressed as a binary number of (M+N) bits as shown in . If the address is attached as shown by arrow 24 in Figure 3, ・5th
In figure (a), the lower M focus is the pixel unit address value (distance δ1i) from the origin O in the X direction, and the upper N bits are ii! from the origin 0 in the X direction! ii address value in prime units (distance Fi(
t).

The image data 9 is first temporarily stored in the image data buffer 2 shown in FIG. 1 via the data bus 7 and multiplexer 5. It is assumed that the storage address at this time is also the same as that shown in FIG. 5(a). Next, this image data 9 is divided into a plurality of rectangles or rectangles as shown at 9' in FIG. It is equally divided into square blocks, and each block is read out in the direction of arrow 26 in the figure.
The data is rolled out block by block to the virtual storage device 4 via the divider 6 and data bus 8 in FIG. As a result,
The image data 9 is stored in the virtual storage device 4 in blocks as shown in FIG. Although image data 9 and 9' are drawn separately for convenience of explanation, they actually represent the same thing.

In order to realize the above operation, first, each block is divided into 2''L pixels (X direction) x 27 pixels - m (X
direction) (m and n are respectively 0≦m≦M, 0≦n≦
In the block size specifying means 10 of FIG. 1, the user specifies the X-direction block size 14 and the X-direction block size as the values of m and n.

Next, as shown at 9' in FIG. 3, the block adjacent to the origin 0 is set as address O, and an address in block units is assigned in binary numbers in the direction of arrow 25, and this is defined as block position address 16. At this time, the number of blocks in the It can be expressed as a binary number of (k - 1j bits) as shown in (5th occurrence).And when an address is attached as shown in the arrow 25 in Fig. 3, the bit is in the lower part of Fig. 5 (b). The address value (distance!a) in block units from the origin 0 in the X direction, the upper l bit indicates the address value (distance) in block units from the origin 0 in the X direction.Based on this, the image data buffer The first step is to determine which block is to be rolled out from the image data 9 (or 9') temporarily stored in the block size specifying means 10.
The block position address 16 is determined by being specified by the block position address designating means 11 shown in the figure.

Next, once the block position address 16 is determined, the addresses within each block are determined. To do this, as shown in FIG. 4, addresses are assigned in binary numbers to each pixel in order from O in the direction of arrow 27 within each block, with the upper left as the origin OB, and this is defined as intra-block address 17. As a result, the intra-block address 17 can be expressed as a binary number of (m+H) bits as shown in FIG. 5(C).
The lower m bits indicate the address value (distance) in units of pixels from the origin OB of each block in the X direction, and the upper n bits indicate the address value (distance ym) in units of pixels from the origin OB in the X direction. Based on this, for each block specified by the block position address 16, the intra-block address 17 is sequentially specified for one block in the intra-block address specifying means 12 of FIG. Used for addressing for rollouts. Note that this operation is performed in the X direction specified by the block size specifying means 10 and in the X direction block size of 14.15.
This is done by sequentially incrementing addresses for the number of pixels found from 0 using an address counter.

Each image data of a specific block can be specified using the above-mentioned block position address 16 and intra-block address 17, but each image data (of the block corresponding to image data 9 (or 9') on the image take buffer 2) For example, the block indicated by arrow 26 in FIG. 39' cannot be directly specified. For this purpose, the image data address calculation means 13 shown in FIG. 1 converts the block position address 16 and the intra-block address 17 into an image data address 18.

Block position address 16 and intra-block address 17
In order to obtain the corresponding image data address 18, as shown in FIG. What is necessary is to add the X-direction component and the X-direction component of address 17.

The X direction block position address is as shown in FIG.
The X-direction component of the block position address (see Figure 5 [b)] can be multiplied by 2p, that is, the number of pixels in the X-direction of the block, as shown in Figure 7.24. This can be determined by filling in the block position address and inserting the X-direction component of the block position address into the upper bits. Similarly, the X-direction block start address can be obtained by multiplying the X-direction component of the block position address (see FIG. 5(b)) by 2', that is, the number of pixels in the X-direction of the block, as shown in FIG. As shown in Figure 7 25, this means that the lower n bits are filled with O, and the upper β bits are filled with the block position address X.
It can be determined by inserting the directional component. The above processing is performed by the block start address calculation circuit shown in Figure 2.
9.

Next, in the intra-block address separation circuit 20, the intra-block address 17 is separated into the m-bit X-direction component shown in FIG. 5(C) and the n-bit X-direction component shown in FIG. Focus on the top as shown in .27,
and l bits of 0 are inserted.

Then, in the X-direction image data address arithmetic circuit 21, the X-direction block start address 24 and the X-direction intra-block address 26 in FIG. 7 are added, and the X-direction image data address 28 is determined.

Similarly, the X-direction image data address arithmetic circuit 22 adds the X-direction block start address 25 and the y-direction intra-block address 27 in FIG. 7 to determine the X-direction image data address 29.

The X-direction and Y-direction image data addresses 28 and 29 obtained through the above processing are combined into lower bits and upper bits as shown in FIG. 7 and 18 in the image data address combining circuit 23. The corresponding address in the image data buffer 2 is referenced.

By the above operation, the block position address 16 is specified, and the intra-block address is sequentially specified for each block, so that the corresponding block on the image data 9 (or 9') stored in the image data buffer 2 is The address of each image monitor within is specified as shown by the arrow 26 in FIG. 3, and each image data is output to the virtual storage device 4.

FIG. 8 is a diagram showing the relationship between the block position address 16, intra-block address 17, and image data address 18. From the figure, the image data address calculation means 13 of FIG.
The X-direction component of the block position address 16 also becomes the upper focus, and the X-direction component of the block address 17 becomes the lower Biff of the X-direction component of the image data address 18].
Similarly, the X-direction component of the block position address 16 is operated to become the upper bit.

Figure 9 (J1) shows that the image data 9 in Figure 3 is 24x2
This shows the case of 4-16 x 16 pixels, and the 9th issue) is 2'X2'-2X as shown in Figure 10 (11).
8jl! This shows an example in which the image data of FIG. 9(a) is divided into ii element blocks. In this case, the block position addresses are as shown in FIG. 4B, with the underlined bits being the X-direction components and the others being the X-direction components. Further, the intra-block addresses in this case are allocated as shown in FIG. 10(a). In this case as well, the underlined bits are the X-direction components, and the others are the X-direction components.

In such a case, the image data address calculation means 13 of FIG. 1 performs an address conversion operation as shown in FIG. 11(a) corresponding to FIG. 8.

Figure io (bl - (n) shows examples of other blocks for equally dividing the image data of Figure 9 (al),
Correspondingly, the image data address calculation means 13 performs the address conversion operation shown in FIG.

The above operation describes the operation of rolling out image data from the real storage device 3 (FIG. 1) to the virtual storage device 4, but conversely, from the virtual storage device 4 to the real storage bag!
23, only the necessary blocks are read out from the virtual storage device 4 to the image data buffer 2 via the data bus 28 and multiplexer 5, as shown in FIG. At this time, the address specification is done in exactly the same way as during the rollout, and the block position address 1
6 and the intra-block address 17 (Fig. 1), the image is inserted into the corresponding image position,
The data is transferred to the real storage device 3 via the divider 6 and data bus 7.

〔Effect of the invention〕

According to the present invention, one large image can be freely and equally divided into multiple blocks according to its attributes, and by simply specifying the position and size of each block on the original image, You can roll in/roll out. As a result, by rolling in/rolling out only necessary blocks, time loss can be shortened and the virtual memory te:i device can be used efficiently. Furthermore, this eliminates the need to increase the capacity of the real memory, making it possible to downsize the device.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of a virtual storage device for image data according to the present invention, FIG. 2 is a configuration diagram of an image data address calculation means, and FIG. 3 is an explanation of the principle of the image data rollout operation according to the present invention. Figure ff14 is an explanatory diagram of addresses within a block, Figure 5 (
a), (b), and (C) are diagrams explaining the bit configuration of each address. Figure 6 is a diagram explaining the principle of address conversion operation. Figure 7 is:
FIG. 8 is an explanatory diagram of the operation of the image data address calculation means, and FIG.
) is a diagram showing an example of the configuration and division of image data, Figures 10 (+1) to (e) are diagrams showing examples of block shapes, and Figures 11 (a) to (81 are each 12 is a diagram illustrating the principle of the roll-in operation of image data according to the present invention. 1. Address control means; 2. - Image data buffer, 3... Real storage device, 4... Virtual storage device, 9... Image data, 10... Block size specification means, 11... Block position address specification means, 12...・
Intra-block address designation means, 13... Image data address calculation means, 14... X-direction block size, 15... X-direction block size, 16...) Long position address, 17... In-block Address, 18... Image data address, 19... Block start address calculation circuit, 20...
Intra-block address separation circuit, 21...X direction ii!
j@! Address calculation circuit, 22... Y-direction image address calculation circuit, 23... Image data address synthesis circuit.

Claims (1)

[Claims] 1) In a virtual storage control device that performs virtual storage control of image data between a real storage device (3) and a virtual storage device (4), a piece of image data (9) is stored according to image attributes. an address control means (1) that equally divides into a plurality of rectangular or square blocks and controls the address on the image data (9) for each arbitrary block; and the real storage device (3) according to the address data from the means. and image data input/output means (2) for transmitting and receiving the image data (9) between the virtual storage device (4) in units of arbitrary blocks. 2) The address control means (1) controls the image data (
block size specifying means (10) for specifying the size (14, 15) of blocks to be equally divided into the block size (14, 15); 16), and intra-block addressing means (12) for sequentially specifying the address (17) of each pixel in one block having the block size (14, 15). ), and sequentially calculates the address of each pixel in a corresponding arbitrary block on the image data (9) from the block position address (16) and the intra-block address (17), and calculates the address of each pixel in the corresponding arbitrary block on the image data (9) as the image data address (18). Image input/output means (
2) A virtual storage control device for image data according to claim 1, characterized in that it is constituted by an image data address calculation means (13) for outputting image data to an image data address calculation means (13). 3) The image data address calculation means (13) calculates the image data (9) from the block position address (16).
) are the image data addresses (24, 25) of the first pixel of the corresponding block on the image, which are orthogonal to each other.
A block start address arithmetic circuit (19) that performs calculations separately in directions (x, y directions);
an intra-block address separation circuit (20) that separates the intra-block addresses (26, 27) into each block address (26, 27) in the two directions (x direction); , y direction) to sequentially calculate the image data address (28, 29) of each pixel in the corresponding block on the image data (9) in each of the two directions (x, y direction). Image data address calculation circuits (21, 22) and image data addresses (2) for each of the two directions (x, y directions).
8, 29) and the image data address (18).
3. The image data virtual storage control device according to claim 2, further comprising an image data address synthesis circuit (23) which outputs the image data to the image data input/output means (2). 4) Virtual storage control of image data according to claim 1, wherein the image data input/output means (2) is an image buffer that temporarily stores one image of the image data (9). Device.