JPS63155530U - - Google Patents
Info
- Publication number
- JPS63155530U JPS63155530U JP4718587U JP4718587U JPS63155530U JP S63155530 U JPS63155530 U JP S63155530U JP 4718587 U JP4718587 U JP 4718587U JP 4718587 U JP4718587 U JP 4718587U JP S63155530 U JPS63155530 U JP S63155530U
- Authority
- JP
- Japan
- Prior art keywords
- bus
- connector
- sub
- board
- main bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Combinations Of Printed Boards (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4718587U JPS63155530U (sl) | 1987-03-30 | 1987-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4718587U JPS63155530U (sl) | 1987-03-30 | 1987-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63155530U true JPS63155530U (sl) | 1988-10-12 |
Family
ID=30867547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4718587U Pending JPS63155530U (sl) | 1987-03-30 | 1987-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63155530U (sl) |
-
1987
- 1987-03-30 JP JP4718587U patent/JPS63155530U/ja active Pending