JPS63155271A - Reduction processing method for dot pattern - Google Patents

Abstract

PURPOSE:To obtain a reduced dot pattern with natural arrangement by generating OR dot arrays of various sectioning positions, and ANDing them and generating the reduced pattern. CONSTITUTION:When a reduced dot pattern consisting of m/l(=5) bits which is 1/l(l=2) times is generated for an objective (m)(=10)-dot pattern array, the array is sectioned in l-dot units and the sectioning positions are made different like A1-A5 and B1-B5 to obtain OR dot arrays A1-A5, and B1-B5 between those dots. Then the dot arrays A and B are ANDed with each other to obtain the m/l-dot pattern.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Fig. 5) Problems to be solved by the invention Zero means for solving the problems (Fig. 1) Working examples ( a) Description of one embodiment (Figures 2, 3, and 4) (b) Explanation of other embodiments Effects of the invention C Summary] A dot pattern of vertical m dots is converted into a dot pattern of vertical m/l dots. In the dot pattern reduction processing method that reduces the dot pattern to a pattern, a dot pattern of 1 m dots is divided into l dot units 9
By creating multiple logical sum dot strings between two divided dots with different separation positions, and obtaining the logical product between the multiple logical sum dot strings, a reduced pattern with an appropriate arrangement and high quality can be obtained. thing.

[Industrial application field]

The present invention relates to a processing method for reducing a dot pattern used in a device such as a dot printer that expresses a pattern such as a character by a collection of dots.

In dot printers, etc., characters are expressed by a collection of dots, so dot patterns for every two characters are stored in memory. With various demands in recent years, it is required to express not only characters of a fixed size but also reduced characters (called script characters). For this purpose, storing the dot pattern of the reduced characters in memory is
In order to increase the memory capacity, the stored dot patterns are reduced to create reduced character patterns.

In this case, the number of dots decreases, so the print quality deteriorates compared to the original dot pattern.

There is a desire for a reduction processing method that can provide a reduced dot pattern with as little deterioration as possible.

[Conventional technology] FIG. 5 is an explanatory diagram of the prior art.

In the conventional reduction processing method, a dot pattern of m bits in the vertical direction is reduced by 1/1 in the vertical direction, but the dot pattern is reduced by m in the vertical direction for every l bit.
A 1/l reduced dot pattern was obtained by dividing the bit pattern and calculating the logical sum between 92 divided dots.

For example, as shown in FIG. 5 (5), the vertical 10 bits (ff
The dot pattern of l=10) is reduced by 1/2.

In order to obtain a 5-bit reduced dot pattern, a 5-bit pattern, which is 1/2, was obtained by dividing the dots into 2-bit blocks from the top and calculating the logical sum between the dots every 2 bits.

[Problem that the invention seeks to solve]

In such a conventional reduction processing method, the position of the two delimiters is constant, and the arrangement of dots is not taken into account at all.

For this reason, it was not possible to obtain a product of good quality with an appropriate arrangement of dots. For example, as shown in Figure 5), the 16-bit vertical character "F" on the left is changed to the 8-bit vertical character rFJ on the right by 1.
As in the case of reducing by /2.

Since the Y1st and Y2nd of the character rFJ on the left are separated into the same group, they fit into the Y1st of the reduced character rFJ on the right, but the Y88th and Y99th of the character rVJ on the left are not separated into the same group. As a result, there may be an unsightly character at the Y4th and Y5th positions of the reduced character rFJ on the right, with two lines becoming one line on one side and two lines on the other side.

Also, in the pattern shown in Figure 5 (5), if any one of the two dots is on (black), this separator is on (black).
Therefore, when it is reduced, it becomes all black, which is very different from the dot arrangement of the binary pattern.

That is, in the prior art, the dots are reduced without considering the arrangement of the dots in order to prevent the number of on-dots from decreasing due to the reduction, resulting in the problem that patterns with appropriate arrangement and high quality cannot be obtained. was.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dot pattern reduction processing method that can obtain a dot pattern with little deterioration in quality even when reduced.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In the present invention, as shown in FIG. 1 (5), first, a target pattern array of m (=10) dots is examined.

1/l (l=2) times m/l (=5)
) (1 (= 2) to create a Di small dot pattern.
Separate in dot units and the separator position from A1 to A5°B1
-B5, and a logical sum dot sequence A1 to A5 . B1 to B5 are created as shown in Figure 1 (B), and the logical product of dot rows A and B is taken as shown in Figure 1 00, m
/l dot pattern is obtained.

The figure shows 1/2 times, but it is 1/3 times.

It may be 1/4 times... and the OR dot string may also be created in 3, 4... columns depending on l.

[Operation] In the present invention, since the arrangement of the reduced dot pattern becomes inappropriate depending on the position of the 9th division, a plurality of logical sum dot sequences are created by changing the position of 1 division and taking the logical sum, and then the optimal dots for the 9th time are created. These are ANDed to obtain the column.

In other words, in contrast to the conventional idea of minimizing the number of ON dots, this method aims to obtain a natural dot pattern by reducing unnecessary ON dots, and eliminates inappropriate arrangement of dots due to the coincidence of 9-separation positions. .

〔Example〕

(a) Description of an Embodiment FIG. 2 is a block diagram of an embodiment of the present invention, showing a control device for a dot printer.

In the figure, 1 is a processor (CPU) that performs printing control and character reduction control, and 2 is a character pattern generator (
CG), each character pattern is 24 dots vertically x 18 horizontally.
4p is stored in dots, 4p is ROM (read only memory), 3 is 6D is RAM (random access memory), CPU work area 3a, and character data that stores character data to be printed. It includes a buffer y3b and a line buffer 73C that stores one line of expanded character patterns, and has a character reduction buffer 130 in the work area 3a.

4 is a dot print head 9 composed of, for example, a 24-dot wire dot head; 5 is a driver that drives the dot print head 4 based on the dot pattern of the line buffer 3C; 6 is a pass. , CPUI and RAM3°-C, G2. This is to connect the driver 5.

FIG. 3 is a processing flow diagram of one embodiment of the present invention.

Print information given in advance from the host device.

It is assumed that character information that has been edited by the CPUI and has a storage address on CO2 corresponding to a one-character code and designation information such as reduction is stored in the two-character data buffer 13b.

■ The CPU reads the character information from the character data buffer 3b, determines whether it is a reduced character from the designation information of the 2-character information, and
If it is not a reduced character, proceed to step ■.

■ If it is a reduced character, CPUI is the storage address, 9
Access 0G2 and read out one column, in this case, a dot pattern of 3 bytes (24 bits).

■ CPUI displays (2n-1) of the read dot pattern.
)-th dot and 2n-th dot are logically ORed. As shown in Figure 1 (B), the first and second logical sums B1 from the top, the third and fourth logical sums B2. . . . A logical sum dot sequence B (n/2) is generated.

■ Next, the CPU reads out the read dot pattern (2n).
-2)-th dot and (2n-1)-th dot are logically summed. As shown in Figure 1 (5) and (B), the logical sum of the 0th check and the 1st check (there is no 0th check, so it is the 1st dora))
AI, the second and third logical sums A2, and so on, to generate a logical sum dot sequence A (n/2).

■ The CPU is a logical sum dot string A (n/2)
and the logical sum dot sequence B (n/2). That is, the logical product of Al and Bl, A2 and B2, etc. is taken, and as shown in FIG. 1 (QK), the reduced dot sequence C(n
/2) and obtains one reduced dot string 0. The CPUI stores this in the character reduction buffer 3o.

(2) The CPU then checks whether the reduction processing for one character string has been completed, and if it has not been completed, it proceeds to the reduction processing for the next string of the character pattern.

Return to step ■.

(2) On the other hand, when the CPUI determines that the reduction process for one character has been completed, it transfers the reduced character pattern from the character reduction buffer 30 to the line buffer 3C.

■ On the other hand, if it is determined in step ■ that the character is not a reduced character, the CPUI accesses the storage address υCG2,
Write one character dot pattern to line buffer 3C.

■ CPUI after completing step ■ or ■.

It is checked whether character pattern expansion to the line back 13c of that line has been completed, and if not, the next character information is read from the two-character data buffer 3b, and the process returns to step (2).

Conversely, if it is determined that the character pattern expansion for that line has ended, C
The PUI sequentially sends the contents of the line buffer 3C to the driver 5 via the bus 6, drives the driver 5, causes the head 4 to print the contents of the line buffer 3c, and finishes the printing process for one line.

The character pattern reduced in this way is shown in FIG.

The left side of Fig. 4 is the character pattern rFJ before reduction;
The right side of the figure is the character pattern rFJ after 1/2 reduction.

In dot printers, the dots are overlapped in the vertical direction and printed so that they appear continuous, so in reality, the dots in the vertical direction overlap and it is better to reduce the number of dots as in the present invention, which can produce cleaner characters. .

(b) Description of other embodiments In the embodiments described above, alphabetic characters were used as examples, but
Other numbers, symbols, etc. may also be used.

Not only 1/2 reduction but also 1/3 and 1/4 reduction is possible.

In this case 2, for example, in 1/3 reduction, three or two logical sum dot sequences may be generated.

Moreover, it is applicable not only to dot printers but also to other devices.

Although the present invention has been described above with reference to embodiments, the present invention can be modified in various ways according to the gist of the present invention.

These are not excluded from the present invention.

[Effects of the Invention] As explained above, according to the present invention, a sequence of logical sum dots at nine different delimiter positions is generated, and a reduced pattern is generated by logically multiplying these dots.

It is possible to eliminate inappropriate arrangement of dots during reduction due to the delimiter position, reduce unnecessary dots, and obtain a naturally arranged reduced dot pattern.

Further, since it can be realized by logical processing, it has the advantage that it can be realized easily and simply.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a configuration diagram of an embodiment of the present invention. FIG. 3 is a processing flow diagram of an embodiment of the present invention. FIG. 4 is a detailed explanatory diagram of the present invention. FIG. 5 is an explanatory diagram of the prior art. In the figure, 1...CPU. 2...CG (character pattern generator). 3C...Line buffer. Applicant: Fujitsu Limited

Claims (1)

[Scope of Claims] A dot pattern reduction processing method for reducing a dot pattern having m dots in at least one direction to a dot pattern of m/l dots (m>l, m/l is an integer) in one direction. , Separate the m-dot dot pattern in units of l dots, create multiple logical sum dot strings that are the result of the logical sum between the separated dots, each with a different separation position, and divide the dots between corresponding dots in the multiple logical sum dot strings. A dot pattern reduction processing method characterized in that a dot pattern of m/l dots is obtained by calculating a logical product.