JPS63153549U - - Google Patents
Info
- Publication number
- JPS63153549U JPS63153549U JP4556987U JP4556987U JPS63153549U JP S63153549 U JPS63153549 U JP S63153549U JP 4556987 U JP4556987 U JP 4556987U JP 4556987 U JP4556987 U JP 4556987U JP S63153549 U JPS63153549 U JP S63153549U
- Authority
- JP
- Japan
- Prior art keywords
- board
- terminals
- integrated circuit
- hybrid integrated
- twisted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007796 conventional method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4556987U JPS63153549U (fr) | 1987-03-30 | 1987-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4556987U JPS63153549U (fr) | 1987-03-30 | 1987-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63153549U true JPS63153549U (fr) | 1988-10-07 |
Family
ID=30864423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4556987U Pending JPS63153549U (fr) | 1987-03-30 | 1987-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63153549U (fr) |
-
1987
- 1987-03-30 JP JP4556987U patent/JPS63153549U/ja active Pending