JPS63153531U - - Google Patents
Info
- Publication number
- JPS63153531U JPS63153531U JP4604387U JP4604387U JPS63153531U JP S63153531 U JPS63153531 U JP S63153531U JP 4604387 U JP4604387 U JP 4604387U JP 4604387 U JP4604387 U JP 4604387U JP S63153531 U JPS63153531 U JP S63153531U
- Authority
- JP
- Japan
- Prior art keywords
- bent piece
- semiconductor device
- clamped
- substrate
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4604387U JPS63153531U (de) | 1987-03-27 | 1987-03-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4604387U JPS63153531U (de) | 1987-03-27 | 1987-03-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63153531U true JPS63153531U (de) | 1988-10-07 |
Family
ID=30865339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4604387U Pending JPS63153531U (de) | 1987-03-27 | 1987-03-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63153531U (de) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06104294A (ja) * | 1992-09-17 | 1994-04-15 | Nec Corp | リードフレーム |
-
1987
- 1987-03-27 JP JP4604387U patent/JPS63153531U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06104294A (ja) * | 1992-09-17 | 1994-04-15 | Nec Corp | リードフレーム |