JPS63151227A - Viterbi decoder - Google Patents

Abstract

PURPOSE:To improve the decoding processing speed by using a node number and the content of a path memory corresponding to the node number and repeating the acquisition of the node selected as an alive number so as to trace the maximum likelihood path, thereby using the most significant digit in binary number of the node number reached at last as the decoded output. CONSTITUTION:ACS circuits 2(0)-2(n) calculate the pathmetic value as to two paths selected based on a brauchmetric value corresponding to each node from a distributer to select a left alive path and to output path selection signals PS(0)-PS(n). A memory 3 stores the path selection signal over a prescribed number of stages corresponding to each node. A path trace control section 4 repeates the calculation of the node number of a node selected as a left alive path at the pre-stage based on the node number of an optional node and the path selection signal of a path memory 3 corresponding to the said node number over the prescribed number of stages. The node number traced in the path trace control section 4 is stored in the trace memory 5 over the prescribed number of stages and the most significant digit in binary number of the node number of a prescribed stage number of the memory 5 is used as the decoded output.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 9 to 12) Problems to be solved by the invention Means for solving the problems (Figure 1) Function (Fig. 2) Example Configuration of the device according to the embodiment (Fig. 3, Fig. 4) Theory of path tracing 1iA (Fig. 2, Fig. 5 to Fig. 7) Explanation of restart method of path tracing (Fig. Figure 8) Effects of the invention [Summary] Using the node number and the contents of the path memory corresponding to that node number, the maximum likelihood path is determined by repeatedly determining the node number of the side selected as a survivor with the node number. A path tracing Viterbi decoder that traces and outputs the most significant binary digit of the node number reached at the end as a decoded output.

[Industrial application field]

The present invention relates to a path tracing Viterbi decoder.

The Viterbi decoder is used for maximum likelihood decoding of convolutional codes, and selects the path with the closest code distance to the received code sequence as the maximum likelihood path from among multiple known code sequences. It obtains decoded data corresponding to the path that has been sent, and because of its high error correction ability, it is used as a decoder for satellite communications and other applications.

[Conventional technology]

The Viterbi decoder is configured with a distributor, an ACS circuit, and a path memory as main elements. FIG. 9 shows an example of a Viterbi decoder with a constraint length of ~3. In the figure, 1 is a distributor, 2 is an AC
S section 3 is a path memory. Decoded signals I and Q of orthogonal modulation are input to this distributor 1 as received codes,
The distributor 1 calculates a branch metric link for each node from this received code, and sends the branch metric to the ACS unit 2.
give to

The ACS unit 2 consists of ACS circuits 2(0) to 2(3), each corresponding to a node when the code generated by the encoder is expressed in a grid as shown in FIG.
S 2 (0) to 2 (3) each include an adder, a comparator, and a selector. Each ACS circuit 2(0) to 2(3)
In addition to the branch metric value from distributor 1,
Path metric values from other ACS circuits corresponding to two paths that can be selected by the node in the lattice representation in FIG. 0 are respectively input. ACS circuits 2(0) to 2(3) are
New path metric values corresponding to the two paths are calculated by adding the path metric value one symbol before to the input branch metric value, and these path metric values are compared using a comparator to find the one with the smaller path metric value. The selected path is selected as the surviving path, and a path selection signal indicating the selected path and the selected path metric link value are output.

The path memory 3 is to which the path selection signal from the ACS unit 2 is applied and stores the history of the surviving paths, and the contents of the path memory of the history with the minimum path metric value are the decoded output. This path memory 3 can have a structure in which path memory cells each consisting of a selector and a flip-flop are connected in multiple stages, or a structure using a RAM.

FIG. 11 shows a block diagram of a path memory in a conventional example where the constraint length is ~3. In the same figure, 2(0) to 2(3)
is an ACS circuit, and ACS circuits 2(0) to 2(3)
, MSII-MS43 is a path memory cell. Although only three stages of path memory are shown in the figure, the number of stages approximately 5.6 times the constraint length is normally used.

Moreover, the path memory cell MSij (i, j-1, 2,
3...) are each composed of a selector 44 and a flip-flop 45, as shown enlarged downward. The selector 44 performs a selection operation in response to a path selection signal from the ACS circuit, and provides its selection output to the data end of the flip-flop 45. The output signal from the output terminal Q of the flip-flop 45 is supplied to two pass memory cells in the next stage.

First-stage pass memory cells MSII, MS21. 0", 11", "0", and 41" are applied to MS31 and MS41 as initial stage inputs, respectively, and are shifted so as to sequentially transition the internal state in response to the path selection signal. That is, ACS circuit 2(0) to 2 for each decoding cycle
The contents of the path memory cell on the side determined to be the surviving path in (3) are transferred to the path memory cell on the other side using the path selection signal.

FIG. 12 is a block diagram showing a conventional example in which a path memory is constructed using a random access memory (RAM). In the figure, 51 is a first stage input setting section, 52,
53 is a RAM, AD is an address input terminal, DI is a data input terminal, Do is a data output terminal, and 54 is an output processing section consisting of a majority circuit and the like.

This path memory is multiplexed using two memories, and for example, at the node number I corresponding to the path memory cell of the path memory described above, the address of the memory 52 is LI/2J, and 2t1+L. Set the node number of the one selected as the survivor among I/2J,
Also, set the address of the memory 53 to 1, and
from the data output terminal Do of the memory 53 to the data input terminal DI of the memory 53.
Transfer data (path information) to. This is performed for all nodes, and the decoded output is derived from the output processing unit 54. In the next decoding cycle, data (path information) is transferred from the data output terminal Do of the memory 53 to the data input terminal DI of the memory 52. Note that the above-mentioned I/2J does not indicate the maximum integer that does not exceed T/2 and is a Gaussian symbol.

[Problem that the invention seeks to solve]

When the path memory is composed of path memory cells consisting of a selector and a flip-flop as shown in FIG.
It is difficult to achieve high integration like RAM. Furthermore, if the path memory is configured with RAM as shown in FIG. 12, it is possible to highly integrate the path memory,
, the number of accesses to the RAM increases, making it difficult to improve the decoding processing speed. For example, in the case of a decoder with a constraint length of ~7, it is necessary to access the memories 52 and 53 64 times per decoding cycle.

Although it is possible to reduce the number of accesses by lowering the multiplicity, in that case the number of memories increases.

Therefore, an object of the present invention is to provide a RAM that is easy to integrate.
An object of the present invention is to provide a Viterbi decoder using a path tracing method that can improve the decoding processing speed while using the following methods.

[Means for solving problems]

FIG. 1 is a principle block diagram of a Viterbi decoder according to the present invention.

The Viterbi decoder according to the present invention includes a distributor 1 that calculates branch metric values for each node from received codes.
, a plurality of ACS circuits 2 (0
) to 2 (n), each AC
S circuits 2 (0) to 2 (n) calculate path metric link values for two paths that can be selected based on the branch metric values from the distributor 1, compare the calculation results, and select the path metric values for the two paths. A surviving path is selected from the path selection signal P S (0) to P S indicating the selection of the surviving path.
(n), bus selection signal P S (0) ~
A path memory 3 that stores P S (n) over a predetermined number of stages corresponding to each node, a node number N(0) of an arbitrary node;
~N (n) and the path memory 3 corresponding to the node number
The path trace control unit 4 repeats, over a predetermined number of stages, the calculation of the node number of the node selected as a survivor in the previous stage based on the bus selection signals PS(0) to PS(n). A trace memory 5 that stores traced node numbers over a predetermined number of stages.
Equipped with. The most significant binary digit of the node number at a predetermined stage of the trace memo 5 is used as the decoded output.

The ACS section 2 consists of 2 to 1 circuits in the case of a constraint length. For example, when the length is ~4, the ACS section 2 consists of 8 ACS circuits.
Consisting of circuits 2(O) to 2(7), each ACS circuit 2(0)
) to 2(7) correspond to eight nodes, respectively.

The eight nodes are assigned node numbers from 0 to 7, respectively. Each ACS circuit 2 (0) to 2 (7)
From there, bus selection signals P S (0) to P S (7) are applied to the path trace control section 4.

Further, a minimum path metric detection circuit is provided for detecting the minimum path metric value from among the bus metric link values P M (0) to P M (7) calculated by the ACS circuits 2 (O) to 2 (7). In that case, the node number of the node corresponding to the detected minimum path metric value is sent to the path trace control unit 4.

[For production]

The path tracing operation by the Viterbi decoder of the present invention will be explained below with reference to FIG.

Fig. 2 is an explanatory diagram of path trace operation, and in the figure, the node numbers O to 7 of each node (and their binary representation) are shown.
, the path metric value at that node number, and the path selection signal in the path memory corresponding to that node number are respectively drawn. Although it is desirable that the number of stages of the path memory is about 5 to 6 times the constraint length (-4 in this case), only 8 stages are shown in FIG. 2 to simplify the explanation.

First, the ACS circuits 2(0) to 2(7) operate in the same way as those of a normal Bikubi decoder, perform path metric link calculations, compare the calculation results to select a surviving path, and pass the path selection signal P S (0 ) ~ PS (7) (“O” or “1”)
Output. This path selection signal P S (0) to P S
(7) is written to the path memory.

In this case, this path selection signal is the most significant bit (MS
Corresponds to B).

The path trace control unit 4 first selects a node to start tracing and starts tracing. Although any node can be selected as the trace start node, preferably the node with the minimum path metric value is selected.

In FIG. 2, the path metric values 82, 7B,
The minimum node 62 (node number 7) among 76, 64, and 62 is selected as the trace start node.

Now set the node number of the trace start node to N. , (NO=
O~2 is 1, K is the constraint length, and coding rate R=1/2), and this node number N is. Let PSO be the contents of the path memory corresponding to . Here, the subscript corresponds to the number of trace stages, and in FIG. 2, since the memory length is 8 stages, it can take values from O to 7. At the start of this trace, the ACS circuit corresponding to node:No is node:N.

NI ~2−” xpSo + LNo /2j Here, LN/2J means that the transition from the largest integer that does not exceed N/2 is selected as the surviving path, so the next node corresponds to NI Read out the contents of the path memory (path selection signal): PS+.Repeat this operation and trace over the entire length of the path memory to obtain the decoded output from the node number of the node reached at the end.In that case, read the last node number. In binary notation, its M
Let SB be the decoded output.

To explain this in more detail using the explanatory diagram in Figure 2,
In step O, the node number N with the minimum path metric value.

=7 and the latest path selection signal PS which is the content of the path memory corresponding to it.

"1" is read out, and based on these, the above formula is calculated, ie, 4X1+3. =7 is performed, and the node number N1-7 is obtained.

Therefore, in the next step 1, this node number N1-7
and the contents of the corresponding path memory: “1” of PS+
Based on this, the node number N2=7 is determined, and in the subsequent step 2, the node number N2-7 and the contents of the path memory: P
A node number N3-3 is calculated based on Sz=O. Thereafter, the node number N8-4 is calculated in step 7 in the same manner.

When the node number N8 is the last traced, the binary notation of the node number 4 is "100", so the MSB "1" becomes the decoded output. Then, the node numbers in steps O to 7 are written into the trace memory 5 for each step.

Thus, for example, the node number N1 is the node number N.

and the contents of its path memory: PSo.

This means that when the node number is expressed as a binary number, the node: No.
By shifting 1 digit lower and setting the contents of the path memory of node No. PSo to the highest position, node N is derived. That is, the node number 4 (ie, "100") of the last node reached in FIG. 2 is derived from the last three bits of the traced path selection signal. Therefore, the path selection signal after storage becomes the MSB of the node number, which becomes the decoded output.

According to the Viterbi decoding algorithm, the decoded output is originally the LSB of the node number of the last node reached.
(least significant bit) is used.

However, the decoded output in that case is the path selection signal itself read third from the end, and the remaining two traces (12 times, if K is the constraint length) have no effect on the decoded output. Therefore, as the decoded output, MS
When B is used, the number of memory accesses is smaller than when LSB is used to obtain the same decoded output, so high-speed operation is possible. In other words, if the MSB is used for decoding output, if the entire path memory is traced by accessing the memory the same number of times as in the case of the LSB, the path memory length will appear longer, that is, the effective length of the path memory will be longer than the actual bus length. Since it is longer than the memory length, the increase in error rate due to path abort is reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In the path tracing method described above, if the calculation of node numbers for path tracing is performed up to the last node reached in one decoding cycle, the number of accesses to the path memory increases, which reduces the decoding processing speed. In the embodiment described below, in order to solve this problem, there is a high probability that the maximum likelihood path in a certain decoding cycle and the maximum likelihood path in the previous decoding cycle will have almost the same shape.
Focusing on the fact that once the node numbers match between the current cycle and the previous cycle, the subsequent paths are the same, we stop tracing when the calculated node number first matches the node number of the previous decoding cycle. By not tracing to the end, the number of accesses to the path memory is reduced, thereby improving the decoding processing speed.

Figure 3 is a block diagram of an embodiment of the present invention, in which 11 is a distributor, 12 is an ACS circuit, 13 is a minimum path metric detection circuit, 14 is a timing generation circuit, and 15 is a block diagram of an embodiment of the present invention. , path trace control unit, 16 is a path memory, 17 is a trace memory, 18 is a trace state control circuit, 19 is a multiplexer (MPX), 20 is a node number calculation unit, 21 is a comparison unit, 22 is a pointer control unit, 23 is a Trace address counters, 24 and 26 are address control units, 25 and 27
is the data control section. The timing generation circuit 14 outputs a clock signal and a timing signal to be supplied to each section using a high-speed clock signal and a data clock signal. The distributor 11 also calculates a branch metric from the received code a, and sends this branch metric b to the ACS.
This is added to the circuit 12.

The ACS circuit 12 is composed of a number of adders, comparators, and selectors corresponding to the constraint length K of the received code a, operates according to the timing signal C from the timing generation circuit 14, and operates according to the branch metric b and the path one symbol before. add the metric link and the adder, compare the new path metric of the addition output with the comparator, output the smaller bus metric from the selector, add the bus metric e to the minimum path metric link detection circuit 13, Also, a path select signal d indicating the comparison result in the comparator is applied to the multiplexer 19 and the node number calculation section 20. The trace state control circuit 18 operates according to the timing signal from the timing generation circuit 14, and switches the trace state according to the coincidence detection signal i from the comparator 21.

Further, the pointer control unit 22 shifts the pointer indicating the start address of the path memory 16 and the trace memory 17 by one stage for each decoding cycle, so that the trace address counter 23 outputs an address signal at the time of tracing. . From the address control unit 24 to the path memory 1
6 is added to a control signal j such as a write enable signal or a continuation enable signal and an address signal, and the read data β from the pass memo IJ16 is transferred to the data control unit 25, Write data β is added to path memory 16. Further, a control signal m such as a write enable signal and a read enable signal and an address signal n are applied from the address control unit 26 to the trace memory 17, and data (node number) is transferred between the data control unit 27 and the trace memory 17. 0 is transferred. The read node number is applied to the comparison unit 21 via the data control unit 27 and compared with the node number g calculated by the node number calculation unit 20, and the comparison match signal i is sent to the trace state control circuit 1.
Added to 8.

The process of inputting the received code a and writing the path select signal to the path memory 16 is the same as in the conventional example. The path memory 16 and the trace memory IJ 17 are constituted by ordinary random access memories, and as shown in FIG. 4, the start addresses of the path memory 16 and the trace memory 17 are designated by pointers.

This pointer is controlled by the pointer control unit 22 and is shifted by one step in the pointer advancing direction every decoding cycle. A path select signal and a start node number are added to the start address indicated by the pointers in the path memory 16 and trace memory 17. The trace direction is opposite to the pointer advancing direction, starting from the first address indicated by the pointer, and the path select signal and node number in the previous decoding cycle are read out according to the address signal from the trace address counter. . The physical addresses of the path memory 16 and the trace memory 17 are the sum of the trace logical address and the start address determined by the pointer, modulo the bus memory length. Therefore, it is desirable that the path memory length be 2'' stages.

Path Tracing Tips The path tracing operation of the embodiment apparatus will be explained below using FIG. 2 mentioned above.

As mentioned above, in Figure 2, the path metric value is 8.
The minimum node number 7, which is 62, among nodes 2, 78, 76, 64, and 62 is selected as the trace start node.

Trace start node number No. 0, this node number No.
Letting the contents of the path memory 16 corresponding to 5Poo,
At this point, the node number is N. ACS circuit 12 corresponding to 0
is the node number N. This means that the transition from I is selected as the surviving path, and the next node number is N. The bus select signal PSo+ of the contents of the path memory 16 corresponding to the path memory 16 is read out. Repeat these operations.

Note that L N, , / 2 J means the largest integer not exceeding Noo/2.

In FIG. 2, step 1 is the node number N with the minimum path metric. . -7 and its corresponding path memory 1
6, the latest path select signal 5Pbo “
1'' is read into the node number calculation unit 20, and the calculation according to equation (1) is performed to obtain 4X1+3=7, so the node number N.I-7 is calculated.

The next step 2 is this node number N. ,=7 of the path select signal SPo+ of the contents of the path memory 16 is read out, and the node number N is read out. 2-7 is calculated. The next step 3 is the path select signal SP of the contents of the path memory 16 corresponding to the node number N (12), and the “
0'' is read and the node number N.3-3 is calculated. Similarly, in step 8, the node number N.B=
4 is calculated.

This node number N. If 1l-4 is the last trace,
4=“100”, the MSB (most significant pit) “1” becomes the decoded output. And step 1~
8 is written to the trace memory 17 at each step.

As mentioned above, in general, in a Viterbi decoder, there is a high probability that the maximum likelihood path obtained in a given decoding cycle is almost the same as the maximum likelihood path in the previous decoding cycle. In other words, there is a high probability that it will be the same as the maximum likelihood path in the previous decoding cycle shifted by one stage and one transition added to it.

FIG. 5 is an explanatory diagram of a path trace, showing a path trace in a decoding cycle following the decoding cycle of FIG. 2. By adding the latest path select signal to the beginning, the contents of the path memory become the contents shown in FIG. 2 shifted by one stage. Also, the passmet link values in this decoding cycle are 19.1B, 14.5, O
Tracing is started from node number 1, which is the smallest 0 among them. When obtaining the node numbers in the same manner as in FIG. 2, in steps 1 to 8, Noo"=0, NoI=4,
Noz=6.

No5-7, Naa"' 3, No5=I
, No.6=O.

N11? = 0, N an = 0. And the last node number N. Since 8=0, that M
SB “0” is the decoded output.

Each node number is written to the trace memory 17, but when compared with the content of the trace memory shifted by one stage in the previous decoding cycle, node number 7 matches in the third decoding cycle, and subsequent node numbers are all the same. In other words, when the node number in the previous decoding cycle and the node number in the current decoding cycle match, the subsequent trace is discontinued and the trace is traced one step before the last node number in the previous decoding cycle. It is possible to obtain the decoding output by using the node number as the last node number of the trace in the current decoding cycle.

In such a tracing process, the node number calculation unit 2
The comparison unit 21 compares the node number g calculated in step 0 with the node number in the previous decoding cycle read from the trace memory 17, and if they do not match, writes the calculated node number g to the trace memory 17. , node number g,
When h matches, a signal i is applied to the trace state control circuit 18 to abort the trace and move to the next control state.

According to experiments, the average number of traces is two or less unless the line error rate becomes extremely bad.

FIG. 6 shows an operation time chart of path tracing, in which the number of tracings per decoding cycle is set to two.
Therefore, the decoding cycle is divided into I10 state, trace state 1, and trace state 2. Further, when the constraint length is set to 7, the path select signal from the ACS circuit becomes 64 bits, and the case is shown in which the path select signal from the ACS circuit is written into the bus memory in 4 times of 16 bits each. Therefore, two 8-bit/word random access memories are required as path memories.

Bus select signal PS, 0 and trace start node number N from the ACS circuit. . As described above, the path select signal PS (10) is written four times in 16 bits each as shown by the arrows, and the latter two times are written in the I10 state.

Also, in this I10 state, the decoded output (the last node number MSB of the trace) is read from the trace memory,
Next, the trace start node number Noo is written into the trace memory. Further, the node number NO+ is calculated based on the above-mentioned equation (1) using the trace start node number N0° and the path select signal PSII+1.

Referring to FIG. 3, the path select signal d is output from the ACS circuit 2, the trace start node number f is output from the minimum bus metric detection circuit 13, and the node number calculation unit 20 outputs the trace start node number f based on equation (1). The node number g is calculated. Also, the path select signal d is sent to the multiplexer 19.
The data is added to the path memory 16 as write data l via the data control unit 25. At this time, the pointer flilJ
Since the start address of the path memory 16 and trace memory 17 is specified by the pointer by the m section 22, the 64-bit path select signal is sent to that address.
It is written in four parts of 16 bits each. Further, the trace start node number f is added to the trace memory 17 from the node number calculation section 20 via the data control section 27.

Node number N. When 1 is calculated, the corresponding path select signal PSo+ is read from the path memory in trace state 1, and the node number N of the previous trace result is read from the trace memory. 1' is read. In this case, the address signal from the trace address counter 23 controlled by the trace state control circuit I8 is
The signal is added to the path memory 16 and the trace memory 17 via the address control units 24 and 26, respectively, and the path select signal and node number are read out.

Then, the node number N (I) calculated previously and the read path select signal PSo+ are used.
oz is calculated, and in the meantime, the node numbers N, .

A comparison of No and ' is made. This is done by comparing the node number g calculated by the node number calculation unit 20 with the node number (2G) read out from the trace memory 17 in the comparison unit 21, and if they match, the signal Since i is added to the trace state control circuit 18,
Transition to next control state. Then, in the next decoding cycle, the trace start node number is N. It is carried out from

If the comparison does not match, tracing is further continued. That is, the calculated node number N. The path select signal PSO2 corresponding to PSO2 is read from the bus memory in trace state 2, the node number NO3 is calculated, and the node number N of the previous trace result read from the trace memory. 2' and the calculated node number N. 2 is compared. In case of a comparison match, the next trace start node number N,. The above operations are repeated.

Although FIG. 6 shows a case where tracing ends in one decoding cycle, FIG. 7 shows a case where tracing does not end. Sequential node numbers starting from trace start node number Noo. + + NO2+ When Nox is calculated and the node numbers are compared in trace state 2,
Node number N. 2 and node number No. 2' do not match, tracing will continue in the next decoding cycle. In that case, tracing is prohibited in the next decoding cycle I10 state, and reading of the decoding output and trace start node number. writing and path select signal PS
,.

The latter half of the process is written. Then, in the next trace state 1, the node number N. The path select signal PSO3 corresponding to 3 is read out, and the previous node number N is read out. 3
' is read, and in the next trace state 2, node number N is read. A comparison of 31NO3' is made.

□1 expression of path tracing.

In this way, when tracing does not end in one decoding cycle, there are three possible restart methods for starting the next trace in the decoding cycle where tracing has ended. In FIG. 8, (a) to (C) are explanatory diagrams for restarting path tracing, respectively, and are for decoding cycles 0, 1, 2, . ...
Let N be the starting node number of the trace in . 0, N,
, 1 N2. ..., restart method 1 is (a)
As shown in , the previous 1 race (trace that did not end in one decoding cycle) restarts from the trace start node selected in the next decoding cycle of the decoding cycle in which it started, and in decoding cycle O. Trace start node number N. . Suppose that the trace starts from and ends in decoding cycle 2, then the next trace starts from the trace start node number N1o selected in decoding cycle I,
When the trace in this case ends in one decoding cycle,
The next decoding cycle 2 starts from the selected trace start node number N2°.

In restart method 2, as shown in (b), the decoding cycle where the previous trace ended (or the next decoding cycle)
It restarts from the trace start node in
As in the previous case, the selected trace starting node number N in decoding cycle 0. Trace from 0,
If the process ends in 3 decoding cycles of decoding cycle θ~2,
Trace start node number N + o, Nz selected in decoding cycle 1.2. is written into the trace memory in the I10 state, and tracing is started from the selected trace start node number N3° in the next decoding cycle 3.

In restart method 3, the trace is restarted from the trace start node in the decoding cycle where the previous trace ended (or the next decoding cycle). However, in a decoding cycle in which the previous trace has not been completed, writing to the trace memory in the I10 state is performed by writing a dummy number instead of the trace start node number. As in the previous case, the trace start node number N. When the trace started from 0 ends in 3 decoding cycles of decoding cycles O to 2, the trace start node number N, selected in decoding cycle 1.2. , instead of Nzo, a dummy number indicating a non-existent node number is written in the trace memory in the I10 state, and in the next decoding cycle 3, the l-race is started from the selected trace start node number N3°. It is something to do. If this trace also does not end in one decoding cycle, a dummy number is written in the trace memory instead of the trace start node number N4o selected in the next decoding cycle 4, and the decoding cycle at the end of the trace or the next The trace will be started from the selected trace start node in the decoding cycle.

The above-mentioned restart method 1 has a somewhat complicated configuration due to the storage of the trace start node number and path select signal.

Furthermore, when E s /N o (signal-to-noise ratio) is degraded, the effective length of the path memory becomes shorter, and therefore the BER (bit error rate) is degraded to the extent that it is.

Furthermore, restart method 2 has the simplest configuration. However, unlike restart method 1, path tracing is not performed completely, so when Es/N is poor, the BER deterioration becomes relatively large.

Furthermore, restart method 3 has a somewhat more complicated configuration than restart method 2, and the number of traces increases. However, the BER is improved compared to restart method 2.

〔Effect of the invention〕

According to the present invention, it is possible to improve the decoding processing speed while using a RAM that is easy to integrate.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of path tracing, Fig. 3 is a block diagram of an embodiment of the invention, and Fig. 4 is a block diagram of the principle of the present invention.
FIG. 5 is an explanatory diagram of address control, FIG. 5 is an explanatory diagram of path tracing, FIGS. 6 and 7 are operation time charts of path tracing, and FIGS. 8(a) to (C) are diagrams of restarting path tracing.
FIG. 9 shows a conventional Viterbi decoder, FIG. 10 is an illustration of a lattice representation, and FIGS. 11 and 12 show a conventional path memory. 1 1 is a distributor, 2 is an ACS circuit, 3 is a path memory, 4 is a path trace control unit, 5 is a trace memory, II is a distributor, 12 is an ACS circuit, 13 is a minimum path metric detection circuit, 14 is a timing generator circuit, 15 is a path trace control section, 16 is a path memory, 17 is a trace memory, 18
19 is a trace state control wholesale circuit, 19 is a multiplexer, 20 is a node number calculation section, 21 is a comparison section, 22 is a pointer control section, and 23 is a trace address counter.

Claims (1)

[Claims] A distributor (1) that calculates a branch metric value for each node from a received code, and a plurality of ACS circuits (2) provided for each node, each of which is connected to the distributor. calculates path metric values for two paths that can be selected based on branch metric values from , and selects a surviving path from the two paths by comparing the calculation results, and a path selection signal indicating the selection of the surviving path. a path memory (3) that stores the path selection signal in a predetermined number of stages corresponding to each node; A path trace control unit (4) that repeats calculating the node number of a node selected as a survivor over a predetermined number of stages, and a trace memory (5) that stores the node number traced by the path trace control unit over a predetermined number of stages. A Viterbi decoder comprising: a Viterbi decoder configured to output the most significant binary digit of a node number in a predetermined stage of the trace memory as a decoded output.