JPS63151218A - Digital pll circuit - Google Patents

Abstract

PURPOSE:To reduce jitter and to quicken the pull-in speed by not applying PLL control when a phase difference between a PLL output and an input signal is within a prescribed range but applying the PLL control quickly when the difference is beyond the prescribed range. CONSTITUTION:A biphase clock generating circuit 12 generates a biphase clock of phases '0' and + or - from a master clock MCLK and supplies it to a selector 13. When the phase difference between the PLL output and an input signal fin is within a prescribed range, a phase comparator circuit 11 gives no pulse. As a result, the selector 13 keeps an output of clocks (either phase '0' or phase + or -) so far and no PLL control is applied. When the phase difference between the PLL output and the input signal fin exceeds a prescribed range, the phase comparator circuit 11 outputs a pulse and the selector 13 applies the changeover PLL control from the phase clock to other phase clock. Thus, when the phase difference between the PLL output and the input signal is within a prescribed range, since no PLL control is applied, the jitter width is reduced and when the phase difference exceeds a prescribed range, since the PLL control is applied instantly, the pull-in speed is much quickened.

Description

[Detailed Description of the Invention] [Summary 1] It is a digital PLL circuit, and if the phase difference between the PLL output and the input signal is within a predetermined range, no control is performed, and if the phase difference is outside the predetermined range, control is not performed. Perform PLL control promptly to achieve high-speed response.

[Industrial Application Field] The present invention is a digital PLL (Phase loc
kLoop) circuit, and more specifically, relates to a digital PLL circuit that enables high-speed response.

When input data is stored in a storage device such as a magnetic disk, the master clock and the input data are generally asynchronous, and it is impossible to maintain correspondence as is. Therefore, it is necessary to synchronize the input data with the basic clock (master clock) that operates the system. Digital PLL circuits are used for this purpose. In recent years, there has been a need to improve the responsiveness of digital PLL circuits due to the need to handle human foot data at high speed.

[Prior Art] FIG. 4 is a dimensional diagram showing an example of a conventional configuration of a digital P L 1 circuit. The operation of the circuit shown in the figure will be described below with reference to timing charts 1 to 1 shown in FIG.

The master clock MCLK shown in FIG.

It is converted into an O-phase and π-phase synchronous clock as shown in (c) and output. Selector 2 has these O phase locks and π
Which of the phase clocks selects one and outputs it. That is, each time a pulse is output from the Q output of the flip-flop 3, the synchronization clock is sequentially switched from O→π→O, . . . .

First, the advance control operation will be explained. When the input signal [in as shown in (d) enters the differentiating circuit 4, the differentiating circuit 4 receives the rising edge of the input signal fin and generates a differentiated pulse as shown in (1). Here, the differentiating circuit 4 is composed of two D-type flip-flops and one AND gate, and the clock at this time is O shown in (b).
A matching lock is used.

The differential pulse generated by the differentiating circuit 4 enters the clock input CK of the flip-flop 5 and latches the "1" level of the PLL output (see (bo)) at this time.At this time, it is latched by the flip-flop 5 and the Q The signal outputted from the output (see (g)) contains phase information (in this case, phase advance) of the PLL output horn and is /V.The Q output of the flip-flop 5 is
Up (U)/Down (D) of up/down counter 6
The up/down counter (hereinafter abbreviated as "U/D counter") 6 is put into an up-counting state. Then, the U/D counter 6 counts the output pulses of the differentiating circuit 4.

The output of the U/D counter 6 reaches the predetermined upper limit value [1
Then, a carry signal as shown in the 1V Lee/Borrow output C/B mechanism of the U/D counter 6 is output. This carry signal is the differential mouth that continues! 87, and the differentiating circuit 7 outputs a pulse as shown in (J). This pulse enters the flip-flop 3 and switches the selector 2 from the previous ○ phase lock to the π phase clock. As a result, the AND gate 8 outputs a beg pulse (shown with diagonal lines in (R) in the figure). (pulse) is masked by the output of the differentiating circuit 7. As a result, the PLL output is controlled in a delayed direction.

The output clock of the AND gate 8 passes through a 1/N frequency divider 9 and becomes a PLL output as shown in (e).

Next, the delay control operation will be explained. When an input signal fin as shown in (d)' enters the differentiating circuit 4, the differentiating circuit 4 generates a pulse as shown in (f)'. At this time, as the clock for operating the differentiating circuit 4, the O-phase lock shown in (b) is used.

The differential pulse generated by the differentiating circuit 4 enters the clock input CK of the flip-flop 5 and latches the "O" level of the PLL output (see (e)') at this time. The signal output from the Q output (see (g)') includes phase information of the PLL output (in this case, delayed phase).The Q output of the flip-flop 5 is
The up (U)/down (D) switching input U/D of the U/D counter 6 is entered, and the U/D counter 6 is placed in a down count state. Then, the U/D counter 6 counts down the output pulses of the differentiating circuit 4.

When the output of the U/D7'J counter 6 reaches a predetermined lower limit value -0, a borrow signal as shown in the carry/borrow output C/B mechanism of the U/D counter 6 is output. This borrow signal is differentiated by the following differentiating circuit 7, and the differentiating circuit 7 outputs a pulse as shown in (x)'. This pulse enters the flip-flop 3 and switches the selector 2 from the previous O-phase lock to the π-phase clock.

As a result, the number of pulses output from the AND gate 8 increases by (P)'. As a result, the PIL output is controlled in the forward direction. Note that the output clock of the AND gate 8 passes through the 1/N frequency divider 9 and is converted to P as shown in (e)'.
It becomes LL output.

[Problems to be Solved by the Invention] As mentioned above, the conventional digital PLL circuit compares the phase of fin and the PLL output every time the input signal fin rises, and then uses the phase information as a time constant counter (U/D counter 6).
), and PLL control is performed by switching the O-phase and π-phase clocks only when the count value reaches the upper and lower limit set values. Therefore, if the time constant of the time constant counter is increased, the jitter suppression effect becomes greater, but there is a problem in that the pull-in speed becomes slower.

The present invention has been made in view of these points, and
Digital PL with small jitter width and fast pull-in speed
The purpose is to provide an L circuit.

Means for Solving Problem L] FIG. 1 is a block diagram of the principle of the present invention. In the figure,
11 detects whether the phase difference between the PLL output and the input signal f in is within a predetermined range, and does not output a pulse if it is within the predetermined range, but only when it exceeds the predetermined range. A phase comparator circuit 12 generates a pulse, and 2 generates a two-phase clock of O phase and π phase from the master clock MCLK.
Phase clock generation circuit 13 is the two-phase clock generation circuit 1
14 is a 1/N frequency divider that divides the output of the selector 13 by N. Part 1/
The output of the N frequency divider 14 becomes the PLL output.

[Action PLL When the phase difference between the L output and the input signal fin is within a predetermined range, the phase comparator circuit 11 does not output a pulse. As a result, the selector 13 selects the clock (O
phase or π phase), and PLL control is not performed. Next, when the phase difference between the PLL output and the input signal fin exceeds a predetermined range, the phase comparison circuit 11 outputs a pulse, and the selector 13 switches the previous phase clock to another phase clock and performs PLL control. conduct. As described above, according to the present invention, when the phase difference between the PLL output and the input signal is within a predetermined range, PLL control is not performed, so the jitter width can be reduced, and when the phase difference exceeds the predetermined range, Because it immediately performs PLL control, it has the advantage that the pull-in speed is extremely fast.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. Components that are the same as in FIG. 1 are designated by the same reference numerals. In the figure, 21 is a differential circuit that generates a differential pulse from the master clock MCLK, and 22 is a differential circuit that generates a differential pulse synchronized with the master clock from the input signal fin. The differentiating circuit 21 is a D type flip-flop (hereinafter F
(abbreviated as "F") and an AND gate.
It is composed of a.

23 is a D type FF which latches the output of the differentiating circuit 21 at the rising edge of the input signal fin, and its negative output is input to the AND gate 22,1. 24 is a D type FF that latches the PLL output at the rising edge of the input signal fin, and its Q
The output is input to one input of the AND gate 25. The other input of AND gate 25 has three people, AND GUT 2.
Contains the output of 2a. The output of the AND gate 22a is also input to the clock input CK of the D type FF 26.
The Q output of the D type FF is given to the selector 13 as an O-phase and π-phase clock switching signal. 31 is an ant game 1 which receives the selector 13 output and the AND GO 1 to 25 outputs, and its output is input to the 1/N frequency divider 14. The operation of the circuit configured as described above will be described below with reference to timing charts 1 to 1 shown in FIG.

The master clock MCLK shown in FIG. 3 (a) enters the two-phase clock generation circuit (b).

The O-phase lock shown in (c) is converted into the π-phase clock and output. The selector 13 receives these two-phase clocks and outputs an O signal every time a switching signal is generated from the D-type FF 26.
→π→O... The synchronization clock is sequentially switched.

First, the delay control operation will be explained. At this time, PLI
- It is assumed that the output is synchronized with the O-phase lock as shown in (d). The differential circuit 21 advances the phase.

A differential pulse A as shown in <e) is output regardless of the slow phase. The control mode differs depending on whether the rising edge of the input signal fin falls within the width of the differential pulse A. In the case of delay control, the PLL output shown in (2) rises later than the input signal fin shown in (2).

The D type FF 2nd stage output a, the 3rd stage output of the differentiating circuit 22, and the output C of the D type FF 23 are (g), (
H) and (S), the AND gate 22a takes the AND of these inputs a, b, and c, so its output d
is as shown in (nu). This pulse d inverts the output of the D type FF 26 and switches the output clock of the selector 13 from the O phase to the π phase.

At this time, the output of the AND gate 25 remains at the "O" level, so the synchronization pulse immediately after switching from the ○ phase lock to the π phase clock is applied to the 1/N frequency divider 14 as shown in (R). The direction of movement is controlled.

Next, the operation without control will be explained.

In this case, the input signal f'+n rises within the width of the pulse A, as shown in (b)'. D type FF23 is
Since the ll 1 II level of the pulse A is latched at the rising edge of the input signal fin, its 6 outputs C become ``○''.Therefore, in this case, regardless of the a or b signal, the The output (d signal) of 22fl is always LL OII and does not output a pulse as shown in (nu)'.Therefore, the output of D type 26 is not inverted and the selector 13
continues to output the previous O-phase lock.

Next, the case of advance control will be explained. In this case,
The PL-1 output shown in (d) rises earlier than the input signal fin shown in (d).a, b.

The C output horns make noises as shown in (1~)'', kuchi), and (su)'', respectively, and the AND gate 22a outputs a pulse d as shown in (nu)''. This pulse d is The type FF26 is inverted, and the selector switches the previous O-phase lock to the π-phase clock.At this time, since the outputs of ANDGOO 1 to 25 are 1° level, the transition from O-phase lock to π-phase lock = 11 - The synchronizing pulse immediately after switching to the other direction is masked by the AND gate 31 as shown in (R)'', and is not output from the AND gate 31. Therefore, control is performed in the delay direction by the amount of this pulse. Thus, according to the present invention,
When the phase difference between the PLL output and the input signal is within a predetermined range, unnecessary PLL control is not performed, resulting in an effect that the jitter width is reduced. Furthermore, according to the present invention,
When the phase difference between the PLL output and the input signal exceeds a predetermined range, PLL control is immediately entered, so that the pull-in speed becomes faster.

[Effects of the Invention] As explained in detail above, according to the present invention, when the phase difference between the PLL output and the input signal is within a predetermined range, the PLL
If L control is not performed and the specified range is exceeded, P immediately
Since LL control is entered, a digital PLL circuit with a high jitter width pull-in speed can be realized.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention. FIG. 2 is a configuration block diagram showing an embodiment of the present invention; Figure 3 is the timing chart, FIG. 4 is a diagram showing an example of the conventional configuration of a digital PLL circuit. FIG. 5 is a timing chart thereof. In Figure 1, 11 is a phase comparison circuit; 12 is a two-phase lock creation circuit; 13 is a selector, 14 is a 1/N frequency divider. Conventional timing chart Cylinder 5

Claims (1)

[Claims] It is detected whether the phase difference between the PLL output and the input signal is within a predetermined range, and if it is within the predetermined range, no pulse is emitted, and when it exceeds the predetermined range, the pulse is not output. A phase comparator circuit (11) that outputs only pulses, and a two-phase clock generation circuit (11) that generates two-phase clocks of 0 phase and π phase from the master clock (
12), a selector (13) that sequentially switches and outputs the output of the two-phase clock generating circuit (12) every time a pulse is generated from the phase comparator circuit (11);
3) A 1/N frequency divider (14) that divides the output by N, and a PLL that outputs the 1/N frequency divider (14).
Digital PLL circuit for output.