JPS63149676U - - Google Patents
Info
- Publication number
- JPS63149676U JPS63149676U JP1987041019U JP4101987U JPS63149676U JP S63149676 U JPS63149676 U JP S63149676U JP 1987041019 U JP1987041019 U JP 1987041019U JP 4101987 U JP4101987 U JP 4101987U JP S63149676 U JPS63149676 U JP S63149676U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- personal computer
- video signal
- separation circuit
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Digital Computer Display Output (AREA)
- Television Systems (AREA)
Description
第1図はこの考案の実施例であるパーソナルコ
ンピユータおよびテレビ受像機のブロツク図、第
2図は前記パーソナルコンピユータに内蔵される
分離回路のブロツク図、第3図は前記パーソナル
コンピユータの動作を示すフローチヤート、第4
図及び第5図A,Bはテレビの映像信号及びその
垂直帰線消去期間内に重畳される文字多重信号の
構成を示す図、第6図〜第8図は文字多重放送の
表示例、文字データのフアイル及びそのフアイル
の画像処理の例を示す。また、第9図は従来の文
字多重放送受信のためのシステムを示す図である
。
1……パーソナルコンピユータ、3……テレビ
受像機、10……分離回路、31……チユーナ、
104……インターフエイス。
Fig. 1 is a block diagram of a personal computer and a television receiver that are embodiments of this invention, Fig. 2 is a block diagram of a separation circuit built into the personal computer, and Fig. 3 is a flowchart showing the operation of the personal computer. Chaat, 4th
5A and 5B are diagrams showing the configuration of a television video signal and a text multiplex signal superimposed within its vertical blanking period. An example of a data file and image processing of the file is shown. Further, FIG. 9 is a diagram showing a conventional system for receiving teletext broadcasting. 1... Personal computer, 3... Television receiver, 10... Separation circuit, 31... Tuner,
104...Interface.
Claims (1)
号から文字多重信号のみを分離する信号分離回路
を、直接的にインターフエイスに接続したことを
特徴とするパーソナルコンピユータ。 1. A personal computer, which receives a television broadcast video signal and has a signal separation circuit that separates only a text multiplex signal from the video signal, and is directly connected to an interface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987041019U JPS63149676U (en) | 1987-03-20 | 1987-03-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987041019U JPS63149676U (en) | 1987-03-20 | 1987-03-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63149676U true JPS63149676U (en) | 1988-10-03 |
Family
ID=30855631
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987041019U Pending JPS63149676U (en) | 1987-03-20 | 1987-03-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63149676U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03141782A (en) * | 1989-10-27 | 1991-06-17 | Seiko Epson Corp | Text signal receiver |
-
1987
- 1987-03-20 JP JP1987041019U patent/JPS63149676U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03141782A (en) * | 1989-10-27 | 1991-06-17 | Seiko Epson Corp | Text signal receiver |
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