JPS63147071U - - Google Patents
Info
- Publication number
- JPS63147071U JPS63147071U JP4011087U JP4011087U JPS63147071U JP S63147071 U JPS63147071 U JP S63147071U JP 4011087 U JP4011087 U JP 4011087U JP 4011087 U JP4011087 U JP 4011087U JP S63147071 U JPS63147071 U JP S63147071U
- Authority
- JP
- Japan
- Prior art keywords
- recording
- sub
- memory
- receiving device
- image signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000001454 recorded image Methods 0.000 description 1
Landscapes
- Editing Of Facsimile Originals (AREA)
Description
第１図および第２図は本考案の一実施例を示す
ブロツク図、第３図は本考案の実施例における各
部の信号波形を示すタイミング図、第４図ａおよ
びｂは本考案の実施例における出力寸法識別パタ
ーンを付加した受信記録画を示す平面図である。
１…選択回路、２…読出し専用メモリ（ＲＯＭ
）、３…識別パターンアドレス回路、４，５…微
分回路、６…バツフア回路、７，８，９…カウン
タ回路、１０…画信号記録エリア、１１，１２…
出力寸法識別パターン。
Figures 1 and 2 are block diagrams showing an embodiment of the present invention, Figure 3 is a timing diagram showing signal waveforms at various parts in the embodiment of the present invention, and Figures 4a and b are examples of the embodiment of the present invention. FIG. 3 is a plan view showing a received recorded image to which an output dimension identification pattern is added in FIG. 1...Selection circuit, 2...Read-only memory (ROM)
), 3... Identification pattern address circuit, 4, 5... Differential circuit, 6... Buffer circuit, 7, 8, 9... Counter circuit, 10... Image signal recording area, 11, 12...
Output dimension identification pattern.
Claims (1)
ないし縮小記録の出力寸法指定に応じて、前記メ
モリに格納された前記画信号データを所定のクロ
ツクで読み出し且つ所定の副走査線密度で副走査
を行なうフアクシミリ受信装置において、前記出
力寸法指定、前記クロツク、および前記副走査線
密度に対応して予め設定した識別パターンを示す
識別信号を発生するパターン発生回路と、前記画
信号データおよび前記識別信号を順次に選択し受
信記録用の記録信号として送出する選択回路とを
、有することを特徴とするフアクシミリ受信装置
。 The image signal data is temporarily stored in a memory, and the image signal data stored in the memory is read out at a predetermined clock and sub-scanned at a predetermined sub-scanning line density according to the output size specification for full-size recording or reduced-size recording. In a facsimile receiving device for carrying out a facsimile reception, a pattern generation circuit generates an identification signal indicating a preset identification pattern corresponding to the output dimension designation, the clock, and the sub-scanning line density; 1. A facsimile receiving device comprising a selection circuit that sequentially selects signals and sends them out as recording signals for recording reception.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4011087U JPS63147071U (en) | 1987-03-18 | 1987-03-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4011087U JPS63147071U (en) | 1987-03-18 | 1987-03-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63147071U true JPS63147071U (en) | 1988-09-28 |
Family
ID=30853901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4011087U Pending JPS63147071U (en) | 1987-03-18 | 1987-03-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63147071U (en) |
-
1987
- 1987-03-18 JP JP4011087U patent/JPS63147071U/ja active Pending
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