JPS63146522A - Receiver with solid-state memory - Google Patents

Abstract

PURPOSE:To utilize a solid-state memory effectively by recording a received sequentially while it is being updated in a range of the memory capacity at the voice input mode at the receiver side and recording an external voice signal in a range of the capacity of a solid-state memory at the voice input mode at a microphone side on the other hand. CONSTITUTION:The received voice signal is recorded sequentially while being updated in the range of the capacity of a solid-state memory 6 at the voice input mode at the reception side, while the external voice signal is recorded in the range of the capacity of the solid-state memory, by the control of a control circuit 1. An output of a reception signal is stopped tentatively at the voice input mode at the reception side and the reception signal recorded in the solid-state memory 6 is reproduced for a prescribed time before the stop by a reproduction command of the control circuit 1, aud the external voice signal recorded in the solid-state memory 6 is reproduced at the voice input mode at the microphone side.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a receiver with solid-state memory, such as a semiconductor memory, which is capable of recording and reproducing audio of received signals and external audio.

Conventional Technology In recent years, with improvements in audio analysis and synthesis technology and the increase in the degree of integration of semiconductor integrated circuits, the technology of converting analog audio signals into digital signals, recording them in semiconductor memory, and playing them back has come to be adopted in a variety of products. It has become.

For example, it may be something that simply records audio and plays back the content, or something that records the playback signal from a tape recorder on a semiconductor memory and plays back the content. It was said that

Problems to be Solved by the Invention However, the above-mentioned conventional devices are simply substitutes for tape recorders, and only a single device is used, and the solid-state memory cannot be used effectively. There was a problem.

Therefore, the present invention continuously records the contents received by the receiver over a certain period of time in a solid-state memory in an endless manner.
By switching to the playback state, it is possible to listen back to the previous received content, and when not in the reception state, an external audio signal is recorded within a time range corresponding to the memory capacity of the solid-state memory, and the message function is activated by playing back the external audio signal. The object of the present invention is to provide a receiver with a solid-state memory which can also have a function of displaying the presence or absence of recording in the solid-state memory and displaying the remaining amount of time of the memory capacity.

Means for Solving the Problems In order to solve the above problems, the receiver with solid-state memory of the present invention includes a voice analysis and synthesis circuit, a solid-state memory capable of recording and reproducing by the voice analysis and synthesis circuit, and a solid-state memory that can be used for recording and reproducing. a receiving circuit and a microphone for performing audio input; a mode changeover switch for both audio inputs; In the side audio input mode, a control circuit is provided for controlling the external audio signal to be recorded within the capacity of the solid-state memory.

According to the above configuration, the present invention temporarily stops the output of the received signal in the receiving side audio input mode, and reproduces the received signal recorded in the solid-state memory for a certain period of time before the stop, in response to a reproduction command from the control circuit. In addition, when in the microphone side audio input mode, external audio signals recorded in the solid-state memory can be reproduced.

Example Below, regarding a receiver with solid state memory according to an example of the present invention,
This will be explained with reference to the drawings.

FIG. 1 shows a block diagram of the first embodiment. In the figure, 1 is a radio tuner section, 2 is a low frequency circuit, and 3 is a speaker. A switching circuit 4 is provided. This switching circuit 4 switches between the output of a normal received signal by the tuner section 1 and the output of an audio signal recorded in a solid-state memory 6, which will be described later, and outputs it from the speaker 3 via the low frequency circuit 2. It is something. Reference numeral 5 denotes a speech analysis and synthesis circuit for both speech analysis and speech synthesis, and 6 a solid-state memory that stores speech analysis data during speech analysis by the speech analysis and synthesis circuit 5 and reads out the stored data during speech synthesis. The solid-state memory 6 is, for example, a random access memory (RAM) of a semiconductor memory, and is capable of recording and reproducing data for, for example, ten seconds.

7 is a microphone, and an external audio signal collected by this microphone 7 is amplified by a microphone amplifier 8. The external audio signal includes the audio signal received by the tuner section 1 and the contact 51 of the mode changeover switch S1.
-1, and is input to the speech analysis and synthesis circuit. That is, as audio signal sources recorded in the solid-state memory 6, there are a reception signal from the tuner section 1 and an external audio signal from the microphone 7, and the input mode of these two signals can be switched by the input mode changeover switch S1. Here, the tuner section 1 side is set to A mode, and the microphone 7 side is set to B mode.

Reference numeral 9 denotes a control circuit which controls the switching circuit 4, the voice analysis and synthesis circuit 5, a display circuit 1° to be described later, etc., and the input for its control operation is the contact 81- of the mode changeover switch S1. 2, a recording/reproduction switching switch S2, and a switching signal input by a B mode recording switch S3. That is, first, when the mode selector switch S1 is in the intermediate OFF position, the control circuit 9 does not operate at all, and its contact 51-1 is also in the intermediate position, and the audio signals from the tuner section 1 and the microphone 7 are sent to the audio analysis and synthesis circuit 5. There is no input. At this time, the switching circuit 4
is in a normal receiving state in which the received signal from the tuner section 1 is supplied to the low frequency circuit 2 side, but a description of switching the receiving state will be omitted.

Next, a case will be described in which the mode selector switch S1 is switched to the A mode side. In this case, first, the received audio signal received by the tuner section 1 is input to the audio analysis/synthesis circuit 5 through the contact 51-1, and the audio signal can be recorded in the solid-state memory 6. On the other hand, the control circuit 9 receives the A mode signal Toshiteno Ireheru (hereinafter H
A signal (abbreviated as "level") is input, whereby the control circuit 9 is maintained in the switching state in which the switching circuit SW included therein outputs a signal indicating the recording state, and the speech analysis and synthesis circuit 6 is brought into the speech analysis state from the output terminal 1. However, at this time, no signal is output from the output terminal 2 to the switching circuit 4, and the received signal from the tuner section 4 is output from the speaker 3 via the low frequency circuit 2. When the voice analysis and synthesis circuit 5 enters the voice analysis state, the received voice signals are sequentially recorded in the solid-state memory 6.
Here, the received audio signals are recorded one after another until the capacity of the solid-state memory 6 is full, but once it is full, the previous recording is sequentially rewritten, so that within the capacity range (time) of the solid-state memory 6. , the latest received audio signals are recorded endlessly. That is, the audio signals received by the tuner section 1 and outputted from the speaker 3 are simultaneously recorded in the solid-state memory 6 in the latest range over a certain period of time. In such a reception and sequential recording state, when the recording/reproduction changeover switch S2 is pressed, the switching circuit SW in the control circuit 9 is switched, and a command signal from the recording state to the reproduction state is issued. As a result, a switching circuit 4 switching command signal is issued from the output terminal 2 to switch the switching circuit 4 from the tuner section 1 side to the voice analysis and synthesis circuit 5 side, and at the same time, the output terminal 1 sends the voice analysis and synthesis circuit 6 to the voice synthesis circuit 6. When a command is issued, this circuit 6 enters a voice synthesis state, and the latest received voice signal recorded in the solid-state memory 6 for a certain period of time is voice synthesized in the voice analysis and synthesis circuit 6, and then sent to the low frequency circuit 2 from the switching circuit 4. The signal is output from the speaker 3 via the . The reproduction of the received audio signal recorded in this solid-state memory 6 is repeated in the same way over and over again until the next time the recording/reproduction changeover switch S2 is operated and the switching circuit SW is switched and a command from the reproduction state to the recording state is issued. This is for playing back recorded content. Then, when the switching circuit SW issues a recording state command again, the output terminal 2 of the control circuit 9
A signal command for switching the switching circuit 4 is output, the switching circuit 4 is again switched to the tuner section 1 side, and the received signal is directly output from the speaker 3. At the same time, the speech analysis and synthesis circuit 5 returns to the speech analysis state and sequentially records the latest received speech signals in the solid-state memory 6 in the same manner as described above. That is, in this human mode, while outputting the received signal of the tuner section 1 normally, the latest received audio signal for a certain period of time (within the capacity of the solid-state memory 6) is sequentially rewritten and recorded, and the recording/playback is performed. By operating the changeover switch S2, the output state of normal reception is temporarily stopped and the received audio signal recorded in the solid-state memory 6 is reproduced. Therefore, in this A mode, in the receiving state, if there is a broadcast of a broadcast station or other guidance address or destination, for example, if you press the recording/playback switch S2 immediately after, it will be recorded in the solid-state memory 6. It is possible to reproduce the contents that have been recorded.

Next, a case will be described in which the mode selector switch S1 is switched to B mode. In this case, first, an external audio signal input from the microphone 7 side is input to the audio analysis/synthesis circuit 6 through the contact 51-1, and the audio signal can be recorded in the solid-state memory 6. On the other hand, a low level (hereinafter abbreviated as L level) signal is inputted to the control circuit 9 through the contact 81-2, which is the same as when it is OFF, and control in the B mode is possible. Further, in this mode, the tuner section 1 is in a stopped state, so that there is no output from the speaker 3 in the initial state. In this mode, to record an external audio signal, by pressing the B mode recording switch S3, the control circuit 9
A command signal is issued to put the voice analysis and synthesis circuit 5 into a voice analysis state, but the voice analysis state is maintained only while this switch S3 is pressed. By inputting the information, it can be recorded in the solid-state memory 6 by voice analysis by the voice analysis and synthesis circuit 6. Recording to the solid-state memory 6 is limited to its memory capacity, and is set to allow recording for, for example, 10-odd seconds, but of course it is not always necessary to record until the capacity is full.

When the external audio signal is recorded in the solid-state memory 6, the control circuit 9 sends a signal (specifically, A high level signal) is generated, and the transistor "rl is biased through the resistor R1 to ONL,
Power supply ■ to light emitting diode D1. It lights up when 0 is applied through the resistor R2. That is, by lighting the light emitting diode D1, it is possible to notify that the external audio signal is being recorded in the solid state memory 6. Then, when the external audio signal is recorded in this way, by pressing the recording/playback switch S2, the switching circuit SW, which is initially held in the recording state, is switched to the playback state, and the control circuit 9 is switched to the playback state. , output terminal 2
The output terminal 1 emits a command signal to switch the switching circuit 4 to the voice analysis and synthesis circuit 5 side, and also outputs a command signal to put the voice analysis and synthesis circuit 5 into the voice synthesis state from the output terminal 1, thereby generating an external voice signal recorded in the solid-state memory 6. is read out and output as a reproduction signal to the speaker 3. At the same time, the output terminal 3 goes to the L level, and the display circuit 10 outputs a light-off signal, so that the light-emitting diode D1 is turned off. This kind of playback state is recorded/
This continues until the reproduction changeover switch S2 is pressed again, and the audio signal recorded in the solid-state memory 6 is repeatedly reproduced. Then, by pressing the record/playback switch S2, the playback state is stopped, but this state is the state in which the original external audio signal can be recorded, and at this time, the recording to the solid-state memory 6 described above is possible. Since it is in a certain state, the output terminal 3 becomes H level again, and the display circuit 10 operates and the light emitting diode lights up. Further, in this state, if the recording capacity of the solid-state memory 6 is not full, further recording is possible. Therefore, in this B mode, the contents of a simple message are recorded, and the receiver confirms the message status by lighting the light emitting diode D1 of the display circuit 1o, and then presses the record/playback switch S2 to record the message. You can listen to the contents of the message. Here, in order to clearly display the lighting state of the light emitting diode D1, the output signal at the H level at the output terminal 3 is made to blink by repeating the H level and L level. You can also do it like this.

In the embodiment shown in FIG. 1 described above, the control circuit 9 can be constituted by a microcomputer, and one part of the above-mentioned operation in this case will be explained below based on the flowchart shown in FIG. 2.

First, in step 1, the mode is switched to A mode, and when the power is turned on, in step 2, the control circuit 9 becomes the signal system switching command High (that is, the recording state), and the voice analysis and synthesis circuit 5 becomes the voice analysis state, and the solid state memory 6 (step 3). In step 4, it is determined whether the recording in the solid-state memory 6 is full with respect to its memory capacity, and if it is full, in the next step 5, a new received audio signal is recorded while erasing the previous recorded content. , on the other hand, skips step 6 and moves on to the next step 6 until it is full. In step 6,
It is determined whether the recording/reproduction changeover switch S2 has been operated or not. If it has not been operated, the process returns to step 3 and repeats the process. When one operation (that is, a reproduction instruction) is performed, the process proceeds to the next step 7. In step 7, the control circuit 9
becomes the signal system switching command Low (that is, the regeneration state),
The voice analysis and synthesis circuit 5 enters a voice synthesis state and reproduces the recorded voice signal in the solid-state memory 6 (step 8). Then, in the next step 9, it is determined whether or not the record/playback switch S2 has been operated, and if it has not been operated, the process returns to the step 8 above and endless playback is performed repeatedly. In this case, the process returns to step 2 and starts recording again.

Next, in step 1o, the mode is switched to B mode and the power is turned on. In step 11, the control circuit 9 becomes the signal system switching command High (that is, in a recordable state). Then, in the next step 12, it is determined whether or not the B-mode recording switch S3 is being operated. If it is being operated, the voice analysis and synthesis circuit 6 enters the voice analysis state and records the external voice signal in the solid-state memory 6. state (step 13)
. In step 14, it is determined whether the memory capacity of the solid-state memory 6 is full of recording external audio signals. If it is not full, the process returns to step 12, and if it is full, the process moves to the next step 16. In addition, if recording is stopped before the memory capacity of the solid-state memory 6 is full, the process returns to step 12 from step 14, and in this step 12 it is determined whether the switch S3 is turned off, so the step 16 side will be moved to. In steps 15 and 16, it is determined whether the recording/playback switch S2 has been operated or not. If it has not been operated, it is in a playback standby state in step 16, and in a recordable state in step 16, and is not operated (ON). If so, proceed to the next step 17. In this step 17, the control circuit 9 outputs a signal system switching command Lo.
w (that is, a playback state), and the speech analysis/synthesis circuit 6 enters a speech synthesis state to play back the audio signal recorded in the solid-state memory 6 (step 18). Then, in the next step 19, it is determined whether or not the recording/playback switch S2 has been operated. Go back to step 11 above and
It becomes possible to record again.

Next, a description will be given based on FIG. 3 showing a second embodiment. This embodiment is provided with a remaining time display circuit 11 for the audio signal to be recorded, depending on the memory capacity of the solid-state memory 6. Components other than this remaining amount time display circuit 11 are the same as those in the first embodiment, so the explanation thereof will be omitted. However, the control command signal to this remaining amount time display circuit 11 is sent to the output terminals 4 to 4 provided in the control circuit 9. It is output from 7. The operation will be explained below. First, when the voice analysis and synthesis circuit 6 is in the voice analysis state and before the switch S3 is pressed, the output terminals 4 to 7 are at a low level. Assuming that the recording or reproducing time for the solid-state memory 6 is, for example, 16 seconds, the terminal 4 is at a high level for 4 seconds from the moment the switch S3 is pressed, the transistor "r2 is turned on, and current flows through the light emitting diode D2. , lights up.Four seconds after the switch S3 is pressed, the terminal 4 goes from high level to low level, and at the same time, the terminal 5 goes from low level to high level.At this time, transistor Tr3 is turned on, and light emitting diode D3 is turned on. Current flows and the light turns on.The following operations are the same, so switch S
For 0 to 4 seconds after 3 is pressed, the light emitting diode D2.
The light emitting diode D3 lights up for 4 to 8 seconds. The light emitting diode D5 lights up for 4 seconds to 16 seconds. The light emitting diode D5 lights up for 4 seconds to 16 seconds. As described above, since the light emitting diode lights up while moving every 4 seconds, the remaining recording time at the time of audio analysis is displayed. In the voice synthesis state, as in the voice analysis state, the light emitting diode lights up while moving in 4-second increments, so that the remaining playback time at the time of voice synthesis is displayed. A timing chart of the above operation is shown in FIG.

In addition, in this embodiment, the lighting of the light emitting diodes is moved one by one, but in addition, for example, the lighting of the switch S3 is moved.
There is also a display method in which all four lights turn on the moment you press the button, and then one by one turns off every four seconds, or a method in which segments are used to display the remaining battery time in numbers.

Effects of the Invention As described above, according to the present invention, when a receiver broadcasts a broadcast station or other guidance address or destination while listening to the broadcast, it can be stored in the solid-state memory by immediately switching to the playback mode. Not only can the recorded content be easily known by listening back to it, but it can also function as a message machine by recording external audio signals, i.e., simple content, when not in the receiving state, and the solid-state memory can be used effectively. It is something that can be put to good use. Further, if a display circuit is provided to notify the recording state of the external audio signal when it is recorded, the message recipient can be informed of the message state more reliably. Furthermore, if a display circuit is provided to display the remaining time of the memory capacity of the solid-state memory, it is possible to record an external audio signal while watching the remaining amount of time, and to prevent the recorded message from being cut off or vice versa. This eliminates the inconvenience of long silent sections, and it is very convenient to know when the message or recorded content ends during playback.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a partial circuit diagram of one embodiment of the receiver with solid-state memory of the present invention, Fig. 2 is a flowchart showing the same operation, and Fig. 3 is a circuit diagram showing a part of another embodiment. , 4th
The figure is a timing chart. 1... Tuner unit, 2... Low frequency circuit, 3... Old speaker, 5... Audio analysis and synthesis circuit, 6... Solid memory, 7... Microphone, 9... Control circuit, 10... Display circuit, Sl... Mode changeover switch. Name of agent: Patent attorney Toshio Nakao and 1 other person7-
Microphone lO- & child circuit Fig. 1 St-mode F changeover switch S2- Record/re-main switch S3-8 mode recording switch + Fig. 2 Fig. 3 Fig. 4

Claims (3)

[Claims] (1) A speech analysis and synthesis circuit for both speech analysis and speech synthesis, a solid-state memory that stores speech analysis data during speech analysis of this speech analysis and synthesis circuit and reads out the stored data during speech synthesis, and the above-mentioned speech analysis and synthesis circuit. A receiving circuit that inputs the received signal as audio input to the receiver, a microphone that inputs the external audio signal, a mode changeover switch that selects the mode of both audio inputs, and a mode changeover switch that selects the mode of both audio inputs. and a control circuit for controlling the external audio signal to be recorded sequentially while updating it within the capacity of the solid-state memory, while in the microphone-side audio input mode, the external audio signal is recorded within the capacity of the solid-state memory. A receiver with a solid-state memory, characterized in that the control circuit reproduces and outputs the audio signal recorded in the solid-state memory by voice synthesis by the voice analysis and synthesis circuit in response to a reproduction command from the control circuit. (2) Corresponding to recording control of external audio signals into solid-state memory using a microphone, a display circuit is provided to notify the external audio signal recording state according to commands from the control circuit, and the notification display state is used as a reproduction control command from the control circuit. A receiver with a solid-state memory according to claim 1, characterized in that the receiver is configured to stop correspondingly. (3) Claim 1 characterized in that a display circuit is provided to display the remaining memory time when an audio signal is recorded in the solid-state memory, and the display is configured to correspond to the memory time. Or the receiver with solid-state memory according to item 2.