JPS63146294A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the level of noise produced by a peak current supplied in precharge by precharging a data line up to a level of voltage lower than the power supply voltage and reducing the peak level of a charging current supplied in the precharge of the data line. CONSTITUTION:A pair of data lines DL connected with a memory cell 2 are precharged up to a level of voltage lower than the power supply voltage. Then the voltage higher than the precharged voltage is written into the cell 2 selected in a data writing and the data on the cell 2 selected in a data reading is read out to the line DL at one at one side. Thus a potential difference is produced between both lines DL and detected by a sense amplifier. Then peak level of the charging current is reduced when the the line DL is precharged since the line DL is precharged since the line DL is precharged up to the voltage level lower than the power supply voltage. Thus it is possible to reduce the level of noise produced by a peak current in the precharge. At the same time, the data reading speed is increased since a potential difference is immediately produced between voltages of both data lines when the data on the memory cell selected in a data reading is read out to one of both lines.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to semiconductor memory. In particular, the present invention relates to a semiconductor memory in which the voltage of a data line from which data is read from a selected memory cell when reading data is higher or lower than the precharge voltage of the data line depending on the memory cell data.

(Prior art) Generally, one transistor/one capacitor/cell type M
16-bit dynamic random access, which is often used as an OS dynamic system (R. R.A.
M) Ti at 1, 3% source method (+x2V.

+sv, -sv) are adopted. However, since the system becomes complicated for 64 bit dynamic LAN, a 5V single power supply is used, which is easy to configure. According to the Dynamic RAM in 64 which adopts this 5V single power supply system, as the power supply voltage decreases, the amount of charge stored in the memory cell capacitor decreases, and hot carriers frequently generated by peripheral circuits or released from the package are generated. The leakage of accumulated charges due to alpha rays, etc. has a serious effect, and stabilization of operation has become a problem. For this reason, conventionally a precharge signal is used for the data line and T10 line (input/output line).

Boost the word line signal higher than the power supply voltage.

The multi-operation margin was improved by setting the 1" level of these data lines and input/output lines approximately equal to the power supply voltage, and by applying @1 current to the memory cell capacitor at a potential level approximately equal to the power supply voltage. However, in this way, the data line and T10
As g is precharged to almost the power supply voltage, the peak current of the charging current during precharging is large, and this peak current generates a large noise level in the spot wire, causing memory malfunction. There is a fear. Further, when reading data, the voltage of the data line gradually decreases from the precharge voltage at the power supply voltage level.

In this case, if the data in the memory cell is at a high potential.

The voltage of the data line from which this potential is read has a smaller drop than the precharge voltage.If the data in the memory cell is at a low potential, the voltage of the data line from which this potential is read is less than the precharge voltage. The amount of voltage drop will be large, but it will take some time for this voltage to drop by a certain amount.

There is a problem that the operation speed during reading is slow.

On the other hand, a dynamic memory using a balanced differential input sense amplifier as shown in FIG. 7 has been considered in order to detect minute signals read out from memory cells. In this memory, a plurality of memory cells 2 are connected to a pair of data lines Di, , Di, connected to a sense amplifier.
, 2' and one dummy cell s, s' (having the same structure as the memory cell and having about 1/2 the amount of information of the memory cell) are connected. Then, one data line DL (or DI
, ) side memory cell 2 (or 2') and the other data line D
The dummy cell 3' (or 3) on the L (or DL) side is selected at the same time. As a result, the voltage of the data line from which the data of the memory cell is read is fixed according to the data of the memory cell, the voltage of the data line from which the data of the dummy cell is read is fixed according to the data of the dummy cell υ, and the pair of data lines A potential difference begins to occur. However, even in this memory, as the data line and T10 line are precharged to almost the power supply voltage, the peak current of the charging current during precharging is large, and this peak current causes large noise in the stain original line. This may cause memory malfunction. Also, when reading data,
The data line voltage gradually decreases compared to the precharge voltage at the power supply voltage level, but -? Yes, it takes some time for this voltage to drop by a certain amount! There is a problem that the operating speed when protruding is slow.

(Problems to be Solved by the Invention) According to the present invention, as described above, the data line t is precharged to the power supply voltage, and the peak current of the charging current during precharging is large.

This was developed to solve the problem that a large noise level is generated due to this peak current. It is an object of the present invention to provide a semiconductor memory that can reduce the level of generated noise υ and improve the operating speed during reading.

[Structure of the invention]

(Means for Solving the Problem) The semiconductor memory of the present invention precharges a pair of data lines, each connected to a memory cell, to a voltage lower than the power supply voltage, and charges the selected memory cell at the time of data writing to a voltage lower than the power supply voltage. A voltage higher than the precharge voltage is written, and the sense amplifier detects the potential difference between the pair of data lines caused by reading the data of the selected memory cell onto one data line during data reading. If the data in the memory cell selected during reading is at a high potential, the data line from which this potential is read is higher than the precharge voltage, and if the data in the memory cell selected during reading is at a low potential. .

It is assumed that data "1" and "0" are read when the potential of the data line to be read becomes lower than the precharge voltage.

(Function) Since the data line is precharged to a voltage lower than the power supply voltage, the peak current of the charging current during data line precharging is small. υ% Reduction of the noise level that often occurs due to the peak current during precharging. becomes possible. Further, when the data of the selected memory cell is read onto one data line during data reading, a potential difference is immediately generated between the data line and the voltage on the other data line, so that the operating speed during reading is improved.

(Example) An embodiment of the present invention will be described below with reference to one drawing.

In FIG. 1, the MOS transistor Ts*T,1
17 - transistors for precharging the line, each with its drain connected to the power supply VC, and its sources connected to "1" with opposite phases to each other.
°0'' data t-to a pair of data lines DL, DL.

The gate is connected to a precharge clock signal ψ.

A short-circuiting transistor T3 is connected between the pair of data lines DL and DL to bring them to the same potential, and the precharge clock signal ψ is input to the gate of this transistor T. Furthermore, transfer gate transistors T, , T, whose drains are respectively connected to the pair of data lines DL, DL and whose gates are inputted with a clock signal ψ are provided. The respective sources are connected to the drain output terminals 01, 0 . . . of a balanced differential input sense amplifier 1 consisting of transistors T. It is connected to the. The source interconnection points of the transistors T, , T, of this sense amplifier 1 are connected to a reference power supply V3 through a transistor T, whose gate receives a clock signal ψ.

Between the data line DL and the reference power supply V3, there is a transfer gate transistor TM whose gate is connected to word 1iWl, 1, and an information storage detection capacitor cM.
are connected. One memory cell 2 is constituted by this transistor TM and capacitor cM.

Furthermore, gates are connected to the column lines CL between the preamplifier 3 and the data lines Di, DL for transmitting and receiving data on the pair of data DL, DL through the input/output lines I10, Ilo. transfer gate transistors T, , T,. is connected. Also, data & IDL and clock signal ψ.

A capacitor C8 is connected between the two, and a refresher circuit 4 is provided. Also, on the data line DL side, there is also a memory cell 2' similar to the above, a reflex 7:L circuit 4'.
is provided. Note that the memory cells 2 and 2' are actually configured as a memory array in which a plurality of memory cells are arranged.

Next, the read operation of the dynamic memory configured as described above will be explained with reference to the time chart of FIG. First, in the precharge cycle, when the potential of the precharge clock signal ψp reaches the power supply potential Ve,
Transistors T, ~T, are conductive and data lines DL, DL
is Vc - Vth (transistor threshold voltage) potential (
It is charged (precharged) to approximately 4V, which is lower than the power supply voltage Vc. At this time, the potential of the clock signal ψ1 is higher than Vc+Vth, and the 7th position of the clock signal ψ is O.
Since the potential of the data lines DL and DL is V, the potential of the data lines DL and DL is connected to the drain/terminal 0 of the transistors T, , T, of the sense amplifier 1 through the conducting transistor T4-Tlt-.
．． ,0. Because it is connected to.

The drain end 01,0. The potential of is Va-Vth,
Its source potential becomes Ve-2Vth.

Next, when the precharge cycle is completed, a data read cycle is executed. Namely.

When the precharge clock signal ψp is QV, the word line specified by the row address input ('fc, for example, W
Lz)' is selected, and its potential is, for example, Vc+3Vth.
(approximately 8V), memory cell 2 is selected. When “1” is stored in this memory cell 2, the capacitor cM of this memory cell 2 has Ve+2Vth (approximately 7V
) The charge stored at the potential of one data line DL
The data line DLOt is read at Vc-Vth+Δ
(The voltage will be higher than the precharged voltage). This minute potential ΔV is a voltage determined by the ratio of the capacitance connected to the data line DL and the capacitance of the capacitor cM of the memory cell 2. At this time, since the other data line DL holds a precharge potential of Vc -vth, the data +Iit DL,
A potential difference of ΔV will occur between DL. These data lines DL.

The potential of DL is the transistor T, which operates as a triode.
, T, are passed through, and the drain ends of the transistors T, T, of sense amplifier 1 are connected as they are, Os - Ox.
It is transmitted to Next, the potential of the clock signal ψ1 is Vc −2
When the voltage drops to about yth, the transistors T, , T
, are cut off, and the data lines DL, DI, and the drain terminals 01.
0. After the clock signal ψ is separated, the clock signal ψ becomes “l”
level (Vc level), the sense amplifier 1 operates and the drain potential of the transistor T6 becomes approximately Vc - vt.
h+ΔV, ) The drain potential of transistor T is approximately Ov
Therefore, transistor T is on, transistor T
4 is turned off, and as a result, the potential of the data line DL is Vc-Vt.
At h+ΔV, the potential of the data line DL becomes approximately O■. After this, the column address input is determined, and when the specified column line channel reaches "1 level (Vc level), s V" +
Input/output line I10 precharged to 'thN level
, T/6, the transistor T0 of the input/output line I10 is in the cutoff state, so the input/output line I10 holds the potential Vc - vth, but the input/output line I/6 holds the potential Vc -vth.

is the transistor T. ,T, ,T1. Since these input/output lines I1 are discharged to the reference power supply Va through
Data is read out to the preamplifier 3 connected to 0 and Ilo.

Thereafter, the blessing cycle is executed as shown in FIG. That is, the clock signal ψ.

is @1 Luher (VC + 2vth potential) Ninaruto, Vc
-vth+ΔV position of data line DL has transistor T0°T4 cut off, so refresh =
- boosted by capacitor C3 of circuit 4, Vc
-Vth+Δv3 potential. Here, the voltage Δ■3 is determined by the balance between the data line capacitance and the capacitor C1. Now, if ΔV 3〉3 V th, the potential of the word line Wl,1 is Vc+3Vth, so the memory cell 2 (7) + Cyt lc5' Ve+2Vth (about 7V) (D voltage is 11 Rarely,
A memory refresh operation is performed. When the above refresher cycle is completed.

The precharge cycle starts again. That is, first, the word line wLx becomes the 0'' level, and the capacitor cM of the memory cell 2 is separated from the data line DL.

The precharge clock signal ψp is at the Vc11 level, the clock signal ψ1 is at the Vc+Vthi level or higher, and the clock signal ψ
8. When all the long column lines CL become '0''', the data lines DL, DL, and the drain ends 0., 0. of the transistors T, T, become near Vc - Vth 11L. .Also, input/output line 1
10, Ilo Fi, in a separate circuit 9 ■c-v
It is precharged to the th potential and returns to its initial state.

On the other hand, if "θ" is stored in the selected memory cell 2 in the next read cycle.

The potential of the data line T)L is Vc-Vth-Δv2, which is lower than the precharge voltage as shown by the broken line in FIG.
(Δv2 is the data line DL when memory cell 2 is "O""
(potential change amount). At this time, the other data line D
Since l, holds the precharge potential (Vcc - Vth), ΔV2 is immediately applied between data iDI, and DL.
A potential difference will be generated. Therefore, after this, the clock signal ψ does not go to the 11'' level, and when the sense amplifier 1 operates, the data line DL becomes Ov, but the data line DL holds the potential Vc - Vth. Even if the clock signal ψ becomes "11" in the cycle, the data line DL remains blank until t of Ov, and the data line DL is boosted to an appropriate potential, but this level does not particularly affect the operation. The important thing here is 11.
In order to equalize the sense margins of the level and the level HI@0'', it is necessary to determine the level of the clock signal ψ or the value of the capacitor C1 so as to have a potential relationship of Δv':Δ■2.

Although the data read operation has been described above, the data write operation to the memory cell 2 can also be explained in the same way. For example, as shown in the time chart in Figure 3,
When writing different information to the memory cell 2 after it has been read once (this is called read-modify-write mode).

For example, the write signal causes the cyclic signal ψ to be “0” once.
"No, input/output 1T10 is at Vc-Vth potential (approximately 4V
), when the input/output fg Ilo is set to “O” level (OV), the column line CL becomes @1” (Vc: 5V)
Therefore, the data line DL is set from OV to the Vc-Vth potential, and the data line DL is set from the Ve-vth potential to Ov. After a certain period of time, the clock signal ψ becomes ′1
”V HELD FZ Revachi I M DL B Vc-
If the potential is Vth+ΔV4, and ΔV4>3Vth, the potential of word line Wl, 1 is vc+3vth, so the capacitor cm of memory cell 2 has a potential of Vc+2Vth (approximately 7V), which is larger than the power supply voltage Vc (5V). You'll be beaten down.

FIG. 4 shows a word line potential generation circuit for supplying potential to word FjWL. In this circuit, a word line timing signal is passed through a buffer 6 and output as a clock signal ψW. This clock signal ψW is delayed by a certain time by the inverters I, I, and is boosted by the capacitor C2 so that it does not exceed the power supply voltage Vc.
Furthermore, transistor T1. 〜TII p Vc+3V
th wL level tonal, cholera transistor T1. ~Kyou.

discharges the excess charge to the power supply Vc and outputs the clock signal φ
This is to fix the potential of W to t-VC+3vth,
There is no particular need. This clock signal ψW and word line W
L1. WL2. . . , transistors T16-1 . T1゜1. . . are connected to the gates of these transistors 'i', 6-, I'r, , i... and a row decoder 7, , 7 . ,... are transistors T1? whose gates are connected to the power supply Vc, respectively. -1
+ 'r+y-t t... are connected. Also,
These transistors T1. -1 t T%m,'v...
・ A putot strap capacitor cs-t l cs-t l... is connected between the gate and source of the transistor 'r, , -11'r1s- ! Coupling capacitance is naturally generated in the inversion layer of the channel of t..., so this may be utilized.

According to the above circuit, when one, for example, the row decoder 7, is selected and its output is at the @1'' level, and the other decoder outputs are at "0", the gate of the transistor T1°-1 is transferred through the transistor T1?-1. is Vc-Vth”ii,
However, the gate of the transistor T1?1 becomes 10" and turns off. Here, the clock signal ψ
When W becomes °1", the word lines Wl and J become @1", but the capacitor C3-3 causes the transistor TI. -8
Since the gate potential of 'I'S@-1 is increased and the transistor T1,1 is cut off, this transistor 'I'S@-1
The gate potential of the word line W becomes Vc+4Vth or higher, and the word line W
The same potential Vc+3Vth as the clock signal ψW is output to L1.

In the word line potential generation circuit described above, the potential of the selected word line is boosted to Ve+3Vth at once, but this is because the capacitance connected to the word line is large.

It is difficult to raise the voltage to the Ve+3Vth potential at a high speed, and it inevitably becomes slow.Therefore, in Figure 5, the voltage of the word line is changed to
゜- Set the boosted potential low enough to turn on the gate transistor TM (for example, set ve+vth to high level), and set the word line to VC+3 during data writing and refreshing.
A word line potential generation circuit is shown in which the voltage is increased to Vth potential to improve read speed.

In the circuit of FIG. 5, the following circuit is added to the circuit of FIG. 4. In other words, a two-man NAND circuit N into which the clock signal ψW and write write signal are input.
, and three-stage inverters I, ~1. And this inverter 1. a capacitor C4, one end of which is connected to the output terminal of the capacitor C4;
Transistors 'rts t 'r, each provided between the other end and the clock signal ψW and the power supply Vc.
. And this transistor T8. The gate is connected between the gate of the inverter I and the output terminal of the inverter I, and the gate is connected to the power supply Ve.
A transistor T, connected to. is provided. Also.

The gate of transistor T8° is connected to power supply Vc.

Further, the transistor T2. A capacitor C1 is connected between the gate and source of the transistor TIm, but this may be used because a coupling capacitance is naturally generated by the channel inversion layer of the transistor TIm without any special provision.

Next, the operation of the circuit shown in FIG. 5 will be explained with reference to the time chart shown in FIG. 6. First, when the data read state is entered and the word line timing signal becomes "1", the clock signal ψW becomes 11# through the buffer 6.
At this time, inverter I.

Since the output of I, is 10'' and the gate of transistor T1. is also 0°, transistor T1. is off, υ,
Capacitor C4 is separated from clock signal ψW, but is charged to '9 Vc-vth potential by transistor Tts. Therefore, capacitor C4 is connected to clock signal ψ
The primary, which is not the load capacity when W becomes @1″,
After a certain period of time, inverter I! When the output of becomes 11”,
The clock signal ψW is boosted by the capacitor C8,
If the size of this capacitor C1 is set appropriately, the clock signal ψW will be approximately Vc+Vth 11. It becomes the rank. At this time, transistor T1. The gate of T4 is charged to the Vc-Vth potential, but the transistor T4 is in a cut-off state. Here, when the write signal becomes "1", the NAND circuit N3. After a certain delay time tD due to inverters I, ~TI. Since the output of inverter I is 1",
Capacitor C4 and transistor T1. While the source of transistor T, is boosted. is cut off and the transistor T1. Since the gate of Tla is also boosted, this transistor Tla is turned on.
The boosted potential is transmitted to the clock signal through this transistor T. As a result, the clock signal ψW is boosted to the *ve-3vth potential.

Therefore, the selected word 1#W1,1 is boosted by this boosted clock signal ψW.

If the clock signal ψ is set to 1" (Vc+2Vth potential) in tandem with the rise of the boosted voltage on the word line WL1, the data line is boosted through the capacitor C8, and the capacitor CM of the memory cell 2 is The boosted data line DL voltage (Vc+2Vth) is written into.

Note that although the above explanation is for when a write signal is input, this write operation is actually performed also at the time of refreshing. In short, the write signal referred to here is a signal that is the logical OR of the external write signal (f write command) and the IJ7 retrieval signal (signal for generating clocks ψ and r).

Note that in the above embodiment, a voltage higher than the power supply voltage is written to the selected memory cell when writing data, but when reading data, the potential read from the selected memory cell to one data line causes the other In principle, in order to generate a potential difference between the data line and the data line, it is sufficient to write a voltage higher than the precharge voltage of the data line to the selected memory cell during data writing. Instead of writing a voltage higher than the power supply voltage to a selected memory cell.

It is only necessary to provide means for writing a voltage higher than the precharge voltage into the selected memory cell when data 11 is written (
For example, this can be realized by changing the potential of the clock signal ψ and the capacitance value of the capacitor C8 in the above embodiment).

Further, in the above embodiment, the precharge voltage of the data line was set to Vc-VTH (4V), but it may be lower than this, but if it is too low, there will be no margin for sensing operation, so approximately 1V /2■c The higher the value, the better.

〔Effect of the invention〕

As described above, according to the conductor memory of the present invention, since the data line is precharged to a voltage lower than the power supply voltage, the peak current of the charging current during data line precharging is small, and the peak current during precharging is small. This makes it possible to reduce the level of noise generated. Further, when the data of the selected memory cell is read onto one data line during data reading, a potential difference is immediately generated between the data line and the voltage on the other data line, so that the operating speed during reading is improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a MOS dynamic memory according to an embodiment of the present invention, FIGS. 2 and 3 are time charts for explaining the operation of the memory shown in FIG. 1, and FIGS. 4 and 5 are block diagrams of different word line potential generation circuits used in the memory shown in FIG. FIG. 6 is a time chart for explaining the operation of the circuit shown in FIG. 5, and FIG. 7 is a circuit configuration diagram of a conventional MOS dynamic memory. 1...Sense amplifier, 2...Memory cell, 3...
Free amplifier, 4... precharge circuit, 6... buffer. yst y,...low decoder, DL, Di,...
data line. WLz, WLz...word line, CL...column line,
Ilo. Ilo...input/output line, CM, C1-C1...capacitor. T1~T,. , TM...transistor, Va...power supply, Vi...reference power supply, ψp...bridage signal, ψ, ~ψ1. ψW...Clock signal. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2rM Figure 3 - A-1 Ginma to Figure 6

Claims (2)

[Claims] (1) a memory cell array having a plurality of charge retention type memory cells, a pair of data lines to which the memory cells are connected, means for precharging the pair of data lines to a voltage lower than a power supply voltage; means connected to a pair of data lines for writing a voltage higher than the precharge voltage into a memory cell selected during data writing;
1. A semiconductor memory comprising: a sense amplifier that detects a potential difference between the pair of data lines caused when data of a selected memory cell is read onto one data line during reading. (2) The semiconductor memory according to claim 1, wherein the charge retention type memory cell is composed of one transistor and one capacitor.