JPS6314460Y2 - - Google Patents

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Publication number
JPS6314460Y2
JPS6314460Y2 JP3878485U JP3878485U JPS6314460Y2 JP S6314460 Y2 JPS6314460 Y2 JP S6314460Y2 JP 3878485 U JP3878485 U JP 3878485U JP 3878485 U JP3878485 U JP 3878485U JP S6314460 Y2 JPS6314460 Y2 JP S6314460Y2
Authority
JP
Japan
Prior art keywords
main electrode
metal base
semiconductor substrate
electrode
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3878485U
Other languages
Japanese (ja)
Other versions
JPS60163760U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3878485U priority Critical patent/JPS60163760U/en
Publication of JPS60163760U publication Critical patent/JPS60163760U/en
Application granted granted Critical
Publication of JPS6314460Y2 publication Critical patent/JPS6314460Y2/ja
Granted legal-status Critical Current

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  • Thyristors (AREA)
  • Die Bonding (AREA)

Description

【考案の詳細な説明】 本考案は平型サイリスタの固定、特に半導体基
体の平面移動および回転移動を防止する構造に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure for fixing a flat thyristor, particularly for preventing planar and rotational movement of a semiconductor substrate.

従来の平型サイリスタの構成は第1図に示すよ
うに、サイリスタ構造の半導体基体1にろう付に
より低抵抗接着され、半導体基体1と熱膨張係数
の近い値をもつWあるいはMoから成るアノード
電極6、これに滑動接触した金属ベース3、半導
体基体1の他面に低抵抗接着したカソード電極5
およびゲートリード線4、カソード電極5に滑動
接触した金属カバー2から成る。また半導体基体
1の端部は所望の耐圧を信頼性良く得るため、接
合表面安定材7で覆われており、半導体基体1全
体は気密性および絶縁性の高いシール8、金属カ
バー2および金属ベース3からなる気密容器内に
納められている。かかる構成において金属ベース
3とアノード電極6の接触面10、および金属カ
バー2とカソード電極5の接触面11がろう付さ
れておらず金属カバー2と金属ベース3に加わる
圧力によりアノード電極6と金属ベース3を低抵
抗接触させる構造の場合、接触面と水平な方向に
強い外力が半導体基体1に加わると、半導体基体
1は横へずれしてしまう。これにより、加圧して
接触している位置がずれて接触が悪くなつたり、
ゲートリード線4が断線したり、極端な場合は半
導体基体端部に傷がついたりする等、装置の信頼
性が著しく低下する恐れがある。このためこれら
欠点を排除する一方法として第1図内に示すよう
に平面移動防止用のガイド9を設けることが提案
されている。これによつて確かに強い外力に対
し、横方向への半導体基体の移動は防止できる。
しかし実際に装置をオン・オフ動作させる場合、
何回となく導通状態において温度上昇し、非導通
状態において温度が低下する。このため半導体基
体1は、ごく僅かではあるが膨張、収縮を繰返し
半導体基体1が面内において自転してしまう懸念
が生ずる。このような場合ゲートリード線4を半
導体基体1に固定した構成において固定位置が側
方にある場合はゲートリード線4の断線、固定位
置が中央にある場合はゲートリード線4のねじれ
という問題が生じる。
As shown in Fig. 1, a conventional flat thyristor has an anode electrode which is bonded to a semiconductor substrate 1 of the thyristor structure with low resistance by brazing, and is made of W or Mo, which has a coefficient of thermal expansion close to that of the semiconductor substrate 1. 6. A metal base 3 in sliding contact with the metal base 3, and a cathode electrode 5 bonded with low resistance to the other surface of the semiconductor substrate 1.
and a metal cover 2 in sliding contact with a gate lead wire 4 and a cathode electrode 5. In addition, the ends of the semiconductor substrate 1 are covered with a bonding surface stabilizer 7 in order to reliably obtain the desired withstand voltage, and the entire semiconductor substrate 1 is covered with a seal 8 having high airtightness and insulation, a metal cover 2 and a metal base. It is housed in an airtight container consisting of 3 parts. In this configuration, the contact surface 10 between the metal base 3 and the anode electrode 6 and the contact surface 11 between the metal cover 2 and the cathode electrode 5 are not brazed, and the pressure applied to the metal cover 2 and the metal base 3 causes the anode electrode 6 and the metal In the case of a structure in which the base 3 is brought into low-resistance contact, if a strong external force is applied to the semiconductor substrate 1 in a direction horizontal to the contact surface, the semiconductor substrate 1 will shift laterally. This may cause the contact position to shift due to pressure, resulting in poor contact, or
There is a risk that the reliability of the device will be significantly reduced, such as the gate lead wire 4 being disconnected or, in extreme cases, the edge of the semiconductor substrate being damaged. Therefore, as a method for eliminating these drawbacks, it has been proposed to provide a guide 9 for preventing plane movement, as shown in FIG. This certainly prevents the semiconductor substrate from moving laterally against strong external forces.
However, when actually turning the device on and off,
Many times, the temperature rises in the conducting state and decreases in the non-conducting state. For this reason, the semiconductor substrate 1 repeatedly expands and contracts, albeit very slightly, and there is a concern that the semiconductor substrate 1 may rotate within the plane. In such a case, in a configuration in which the gate lead wire 4 is fixed to the semiconductor substrate 1, if the fixed position is on the side, the gate lead wire 4 may be broken, and if the fixed position is in the center, the gate lead wire 4 may be twisted. arise.

本考案の目的は上記した従来技術の欠点をなく
し、半導体基体の平面移動、回転移動を防止し、
信頼性の高い加圧接触平型半導体装置を提供する
ことにある。
The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art, prevent planar movement and rotational movement of the semiconductor substrate,
An object of the present invention is to provide a highly reliable pressure contact flat semiconductor device.

本考案は上記目的を達成するため、アノード電
極と金属ベースに互に対向する周側端部を非真円
形とする欠損部をそれぞれ設け、両欠損部に移動
防止体を嵌合させている。
In order to achieve the above-mentioned object, the present invention provides the anode electrode and the metal base with defective portions whose circumferential ends facing each other are non-circular, and a movement preventing body is fitted into both the defective portions.

本考案の構成および作用効果を第2図に示す実
施例に基づき説明する。
The structure and effects of the present invention will be explained based on the embodiment shown in FIG.

本実施例で第1図に示す従来例と異なる点は、
アノード電極6の周端部の一部に欠損部12を設
けていること、金属ベース3の端部全周に欠損部
15を設けており、その一部は比較的大きな欠損
部13を形成していることである。そしてこれら
欠損部にちようど嵌まり合い、アノード電極6の
平面方向のずれを防ぐことができる様にアノード
電極6の端部全周を囲む様なb図に示す形状の移
動防止体9をアノード電極6と金属ベース3の間
に嵌め合つていることである。すなわち、d図に
示す様に半導体基体1にろう付されたアノード電
極6は一部に設けた欠損部12に対しては移動防
止体9の一部突出部16が、金属ベース3の一部
に設けた比較的大きな欠損部13に対しては移動
防止体9の一部突出部17がちようど嵌り合い、
これによつて位置合わせができ、さらに半導体基
体1の回転を防止できる。なお移動防止体9は
Al,Cu等の加工が容易な金属でも良く、また耐
熱性が良く、加工できるふつ素系樹脂等の無機物
でもかまわない。かかる構成により半導体基体1
の平面移動、さらに回転移動を防止でき、ゲート
リード線4の断線、よじれがなくなるので装置の
信頼性の向上が期待できる。金属ベース3とアノ
ード電極6はその接触面が平坦であるため、両者
間における熱、電気の良好な伝導を確保すること
ができ、平面移動と回転移動を防止したことによ
る特性劣化を伴うことはない。
The difference between this embodiment and the conventional example shown in FIG. 1 is as follows.
A defect 12 is provided in a part of the peripheral edge of the anode electrode 6, and a defect 15 is provided all around the edge of the metal base 3, and a portion of the defect forms a relatively large defect 13. This is what is happening. Then, in order to fit into these defective parts and prevent the anode electrode 6 from shifting in the plane direction, a movement preventing body 9 having the shape shown in Fig. b is installed so as to surround the entire circumference of the end of the anode electrode 6. It is fitted between the anode electrode 6 and the metal base 3. That is, as shown in FIG. The partial protrusion 17 of the movement prevention body 9 fits into the relatively large defect 13 provided in the
This allows alignment and further prevents rotation of the semiconductor substrate 1. Furthermore, the movement prevention body 9 is
It may be a metal that is easy to process such as Al or Cu, or it may be an inorganic material such as a fluorine-based resin that has good heat resistance and can be processed. With this configuration, the semiconductor substrate 1
It is possible to prevent plane movement and rotational movement of the gate lead wire 4, and the gate lead wire 4 is prevented from being disconnected or twisted, so it is expected that the reliability of the device will be improved. Since the contact surfaces between the metal base 3 and the anode electrode 6 are flat, good conduction of heat and electricity can be ensured between the two, and property deterioration due to prevention of planar movement and rotational movement is avoided. do not have.

なお、移動防止体9の位置合わせ用一部突出部
16,17は同一方向に設ける必要性は特にな
く、反応方向にあつてもよい。
Note that the positioning partial protrusions 16 and 17 of the movement preventive body 9 do not need to be provided in the same direction, and may be provided in the reaction direction.

またゲートリード線4を固定している位置は第
2図のような半導体基体の側方にある場合に限ら
ず半導体基体1の中央に設けたいわゆるセンタゲ
ート構造においても本考案を適用でき、同様の効
果が得られる。
Furthermore, the present invention is applicable not only to the case where the gate lead wire 4 is fixed to the side of the semiconductor substrate as shown in FIG. 2, but also to a so-called center gate structure provided in the center of the semiconductor substrate 1. The effect of this can be obtained.

更に、アノード電極を他方の主電極として説明
したが、アノードゲートの場合は、ゲートリード
線とアノード電極が一方の主面に設けられ、カソ
ード電極は他方の主面に設けられることになる。
この場合、カソード電極が他方の主電極として金
属ベースと滑動接触されることになるが、このよ
うな場合でも、カソード電極と金属ベースに欠損
部を設けて移動防止体を嵌合させれば、同様な効
果が得られる。
Furthermore, although the anode electrode has been described as the other main electrode, in the case of an anode gate, the gate lead wire and the anode electrode are provided on one main surface, and the cathode electrode is provided on the other main surface.
In this case, the cathode electrode will be in sliding contact with the metal base as the other main electrode, but even in such a case, if a cutout is provided in the cathode electrode and the metal base and the movement prevention body is fitted, A similar effect can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の加圧接触型平型サイリスタの断
面略図、第2図は本考案の一実施例を示してお
り、aは加工したアノード電極および金属ベース
の断面図、bは移動防止体の上面図、cはbに示
す移動防止体のA−A切断線に沿つた断面図、d
はアノード電極、移動防止体、金属ベースを結合
させた時の断面図である。
Fig. 1 is a schematic cross-sectional view of a conventional pressurized contact type flat thyristor, and Fig. 2 shows an embodiment of the present invention, in which a is a cross-sectional view of the processed anode electrode and metal base, and b is a movement preventive body. c is a cross-sectional view along the A-A cutting line of the movement prevention body shown in b, d
is a cross-sectional view when the anode electrode, anti-movement body, and metal base are combined.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] サイリスタ構造の半導体基体の一主面にゲート
電極と一方の主電極が低抵抗接着され、他方の主
面には、他方の主電極が低抵抗接続され、上記一
方および他方の主電極に金属カバーおよび金属ベ
ースが滑動接触している平型サイリスタにおい
て、上記他方の主電極および金属ベースは互いに
対向する周側端部を非真円形とする欠損部がそれ
ぞれ設けられており、上記欠損部に嵌合する金属
ベースに対する他方の主電極の移動防止体を備え
ていることを特徴とする平型サイリスタ。
A gate electrode and one main electrode are bonded with low resistance to one main surface of a semiconductor substrate having a thyristor structure, the other main electrode is connected with low resistance to the other main surface, and a metal cover is attached to the one main electrode and the other main electrode. and a flat thyristor in which the metal bases are in sliding contact with each other, the other main electrode and the metal base are each provided with a defective portion in which the circumferential ends facing each other are non-perfectly circular, and the other main electrode and the metal base are each provided with a defective portion having a non-perfect circular shape, and the other main electrode and the metal base are fitted into the defective portion. 1. A flat thyristor comprising a movement prevention member for the other main electrode relative to a mating metal base.
JP3878485U 1985-03-20 1985-03-20 flat thyristor Granted JPS60163760U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3878485U JPS60163760U (en) 1985-03-20 1985-03-20 flat thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3878485U JPS60163760U (en) 1985-03-20 1985-03-20 flat thyristor

Publications (2)

Publication Number Publication Date
JPS60163760U JPS60163760U (en) 1985-10-30
JPS6314460Y2 true JPS6314460Y2 (en) 1988-04-22

Family

ID=30546110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3878485U Granted JPS60163760U (en) 1985-03-20 1985-03-20 flat thyristor

Country Status (1)

Country Link
JP (1) JPS60163760U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1322376A (en) * 1998-08-07 2001-11-14 株式会社日立制作所 Flat semiconductor device, method for manufacturing same, and converter comprising same

Also Published As

Publication number Publication date
JPS60163760U (en) 1985-10-30

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