JPS63142842U - - Google Patents
Info
- Publication number
- JPS63142842U JPS63142842U JP3501387U JP3501387U JPS63142842U JP S63142842 U JPS63142842 U JP S63142842U JP 3501387 U JP3501387 U JP 3501387U JP 3501387 U JP3501387 U JP 3501387U JP S63142842 U JPS63142842 U JP S63142842U
- Authority
- JP
- Japan
- Prior art keywords
- signal line
- array
- wired
- negative
- affirmative
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3501387U JPS63142842U (sv) | 1987-03-10 | 1987-03-10 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3501387U JPS63142842U (sv) | 1987-03-10 | 1987-03-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63142842U true JPS63142842U (sv) | 1988-09-20 |
Family
ID=30844112
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3501387U Pending JPS63142842U (sv) | 1987-03-10 | 1987-03-10 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63142842U (sv) |
-
1987
- 1987-03-10 JP JP3501387U patent/JPS63142842U/ja active Pending