JPS63142592A - Multi-dimension access memory - Google Patents

Abstract

PURPOSE:To obtain a memory with a few number of selecting lines and suitable for picture processing or the like by providing a pre-decoder in common to each selection dimension and outputting plural bits of designated dimension at the same time. CONSTITUTION:Data are stored discretely at each other 3-bit to a word line in response to number of dimensions. Other data is stored similarly also to each idle bit. Thus, four 2-dimension data are stored onto one word line. I selecting one of the four data by a decoder 32, a gate 72A is opened and a sense amplifier SA72A or the like is connected to an output line L72 or the like. Then a decoder 40 decodes a segment address and gives an output to an exclusive selection line 38, uses dimension selection signals x, y, s to lead the output of a sense amplifier to a data bus 20 through a selection gate 34 of a selection circuit 16 and a transfer gate 36. Through the constitution above, number of selection lines is less, high circuit integration is attained and this memory is suitable for picture processing or the like.

Description

[Detailed Description of the Invention] [Summary] A decoding method that facilitates multidimensional access in a large-capacity semiconductor memory. Even with conventional processes and circuit technology, it is possible to achieve higher levels of integration and dimensionality.

[Industrial application field]

The present invention relates to a multidimensional access memory, and more particularly to a semiconductor memory capable of simultaneously outputting a plurality of bits in a specified dimension during reading out of a large number of bits read out by selecting an arbitrary word line.

[Conventional technology]

In a semiconductor memory such as a DRAM, when a word line is selected, the stored data of all memory cells belonging to that word line appears on each bit line, and normally one bit of the data is selected by a column address and output to the outside through a data bus. However, if multiple data buses are provided, the column gates can be changed accordingly to output multiple bits at the same time. In order to speed up data processing in image memories and the like, simultaneous reading of multiple bits is particularly required.

When storing two-dimensional or three-dimensional, or n-dimensional, image data in a memory and reading out a plurality of bits at the same time, the following problems arise. Horizontal X in Figure 3,
The figure shows three-dimensional image data of 512 bits each, 8 bits each for vertical Y and depth Z. This is 64 sets of 8 bits arranged in the X direction, and the number of word lines is 64, and the number of bits for each word line (
If you write to the memory cells of each word line of a memory with 8 memory cells (8 memory cells) and 8 data buses (8 bits that can be output simultaneously), just selecting one word line (with one access) Eight direction bits can be read simultaneously. However, to read 8 bits in the Y direction or Z direction, 8
The data must be accessed several times and the first bit, for example, must be extracted each time, which increases the access time.

Image data processing requires tasks such as extracting and processing multiple bits in the X direction, as well as extracting and processing them in the Y and Z directions, and there is a demand for all of these to be executed as quickly as possible and in the same amount of time. .

The mode of extracting a plurality of bits is not limited to the x, y, and Z directions, but also oblique (diagonal) directions, and there is also a demand for extracting in the plane S as shown in FIG. In addition, Fig. 4 (al is 1
It shows 6 x 16 bit two-dimensional image data, of which S is 4 x 4 bit data.

The present inventors have developed a memory capable of simultaneously reading multiple bits in any direction or plane (referred to as dimension). The main part of this memory is a selection circuit interposed between the bit line and the data bus.

In other words, when one word line is selected, the data of all memory cells belonging to that word line (there are n pieces, where the number of bit lines is n) is output to all bit lines, so the data bus is A large number (m) of bytes, etc. are provided, and a specified mode (dimension) is provided between this data bus and the bit line.
If a circuit for selecting m bits in is provided, simultaneous selection in specified dimensions is possible.

Figure 5 is an example of this, where WLi is the 1st word line, BL72
．． BL72 is the 72nd human line pair, 5A72 is its sense amplifier, BL73. BL73 is the 73rd focusing line pair, 5A
73 is its sense amplifier. 20 is the data bus,
There are 2 bytes. 16 is a selection circuit that selects the output of each sense amplifier in designated dimensions (x, y, s) and segments (Bo
=B3) to the data bus 20 (.The selection circuit 16 consists of decoders (X+3'+S decoders) of each dimension arranged for each sense amplifier, each of which has a segment address in common. Receive Bθ~B3,
Further, each of the dimensional control signals x, y, and s is activated when the corresponding control signal is input.

To explain the multidimensional selection procedure using this figure, there are 256 bits in one word line, and these are the 16 bits in the followed by 16 bits in the X direction of Y=1, then Y=
2 (16 bits in the X direction are lined up and bound), then sense amplifier No. 72 SA? 2. In the X direction, the 8th bit of the 4th group (Y=4) is also connected to the 73rd sense amplifier SA? 3 outputs the 9th bit between Bo-B3
indicates the fourth group (fourth segment), the output of 5A72 is transferred to data buses DB8 and DB by X decoder X72.
8, and the output of 5A73 is connected to DB9.
DB 9, and the same goes for the 4th group in the X direction 16.
It is possible to simultaneously output the bisoto to the data bus 20.

Also, the output bits of 5A72 are in the 8th group (X=8
), and that of 5A73 is the fourth bit of the ninth group, so when Bo-B3 indicates the eighth group, the y decoder Y72 converts the output of 5A72 to DB4. Lead to DB4,
Also, when Bo=83 indicates the 9th group, the output of 5A73 is changed by the y decoder Y73 to the same <DB4. By leading to the DBT and doing the same for the others, the 16 bits in the Y direction of each group can be outputted sequentially (simultaneously within the group) to the data bus. The same applies to the 8th side.

FIG. 6 shows an example of an X decoder. Q + −Q 6° Q16 is a p-channel transistor, and Q7 to QI6 are n-channel transistors. If X is H (high), then Q
I6 is off, Q16 is on, and node Nl is L (low), so Q12 is off, Q6 is on, and Q1 to Q4 . Q7～Q
The IO decoder section is enabled and address Bo=83
selects this decoder (83~Bo is 0100
If the fourth group is selected) node N3 is L1, so Q5 is on,
Qll is off, node N2 is H, transfer game
FQ13 + Q14 is turned on and the output of 5A72 is sent to the data bus DB8. D100].

As shown in Figure 5, if a decoder for each dimension is provided at the output end of each sense amplifier (this also applies to each bit line) and the connection with the data bus is controlled, multidimensional access becomes possible. Since the bit line spacing is narrow,
In practice, it is difficult to provide decoders for each dimension within this spacing, and this increases the bit line spacing and may result in a memory with low integration.

This point has been improved in FIG. That is, in Figure 7,
An X+)'+S predecoder is commonly provided to all sense amplifiers, and a decoded output is supplied to each sense amplifier. 30x, 30y, 30s are 16 selection lines each that supply this decoded output, 72x, 72y, 72s...
... is a transfer gate, and 72x is the above Q13+
Corresponds to Q14. X.

y, S predecoder 18 x, 181. 18
Only one s is activated by the signals x, y, and s, and each decoder makes one of the 16 outputs H, and among these 16X3=48, only one H selection line connects the 16 pairs of transfer lines. Turn on the gate and lead the output of the sense amplifier to the data bus.

The output O of the X predecoder selects the 0th segment, the output 1 selects the 1st segment, and so on. Assuming that the data on the word line is as described above, the sense amplifier SAa=SAH6 outputs the Oth segment in the X direction. Therefore, the output O of the X predecoder turns on the transfer gates connecting the outputs of these sense amplifiers and the data buses 0 to Y, and guides the output of SAo'=SA15 to the data buses 0 to F. As mentioned above, the output of the sense amplifier 5A72 is that of the 8th bit of the 4th group in the X direction, so when the dimension control signal X is input and Bo=83 indicates 4, the X predecoder 18x produces an output of 4 ( Output 4 is set to H), transfer gate 72x is opened, and the output of 5A72 is guided to data buses 8, 8. Since the output of 5A72 in the Y direction is that of Pinoto No. 4 in the 8th group, the dimensional control signal y
enters, B.

~When B3 indicates 8, the y predecoder 18y sets the output 8 to H, opens the transfer gate 72y, and guides the output of 5A72 to the data bus 4.7. Furthermore, the output of the 5A72 is for the 6th group bit 0 on the surface S (the 0th group is 16 bits with x=y=o at the upper left corner in FIG. 4, and the 1st group is X=4.Y=
16 bits of O...The fourth group is X=0. Y=4
16 bits...), so when the dimension control signal S is input and Bo-B3 indicates 6, the
8s sets output 6 to H, opens transfer gate 72S, and guides the output of 5A72 to data bus 0.0.

The same goes for the output of the sense amplifier 5A73, x, y
, s predecoder is transfer gate 73x, 73y
, 73s and connects it to the data bus 9, 9 or 4,
Leads to 4 or 1,1.

The selection lines 30x, 30y, 30s and transfer gates 72X, 72y, . occupies the position shown in Reference numeral 10 denotes a cell array, which in this example has 256 word lines WL and 256 pairs of bit lines BL, BL.

A o ” A? is the address to select the word line, B
.

~B3 is a column for selecting bit lines with one set of 16 bits (
segment) address. 22 is a latch.

[Problem that the invention seeks to solve]

In FIG. 5, decoders for each of the various selection dimensions are arranged in each sense amplifier, but this increases the number of decoders and takes up space. Since each type of decoder must fit within the bit line spacing, the space for the decoder is extremely limited and the bit line spacing must be increased. In this method, when extracting N bits in parallel from N8 bits of data using the dimensional method, the number of decoders is kN'' and the number of signal lines is (210g, N + k). If a pre-decoder is provided at , the number of decoders can be reduced to , and the problem of having to accommodate various decoders within the focus line interval is eliminated.

However, kN selection lines are required.

The present invention attempts to improve these problems by using a pre-decoding method to alleviate problems in decoder placement and to reduce the number of selection lines.

[Failure to solve the problem]

The multidimensional access memory of the present invention includes a data bus (20) capable of parallel output of multiple bits, and a data group of multiple bits made up of multiple segments, with the multiple bits as one segment, written into memory cells on one word line. a cell array (10), a decoder (40) that receives segment addresses (B0 to B3) and produces decoded output thereof;
A selection line (38) that receives the output of the decoder, a dimension selection signal (x, y+S) line, a transfer gate (36) that connects the focus line of the cell array to the corresponding line of the data bus, and a transfer gate (36) that connects the decoder output and the dimension selection signal. a selection circuit (16) having a selection gate (34) that generates an output for turning on and off the transfer gate in response to a data bus (20) capable of outputting multiple bits in parallel; A multi-bit data group consisting of a plurality of segments with a bit as one segment is written into memory cells on one word line in a discrete manner according to the selected number of dimensions, and other multi-bit data groups are similarly written into empty memory cells. A cell array (10) to be written discretely into the cell array, and each sense amplifier (10) connected to each human line of the cell array.
SA72A, 5A72B, . . .) to the output line for each bit in the data group (L72, L73, . . .)
...), a decoder circuit (32, 72A, ...) connected according to the group selection bits (C0, C1),
a decoder (40) that receives the segment address (BQ"B3) and produces its decoded output; and the decoder (40).
), a selection line (38) receiving the output of the dimension selection signal line (x
,y.

s), 1- for connecting the output line to the corresponding line of the data bus;
a selection circuit (34) having a transfer gate (36) and a gate circuit (34) which receives the decoder output and the dimension selection signal and generates an output for turning on and off the transfer gate;
16).

C effect] This configuration enables multi-dimensional access, does not take up decoder space, does not require too many lines to be selected, and provides a memory suitable for image processing, etc. .

〔Example〕

FIG. 1 shows an embodiment of the present invention. After all, it is selected in the X, )'+S dimension, and the simultaneous appearance is always 16 bins. Therefore, the data bus 2o has 16 pairs. The predecoder is common to each selection dimension, so that only 16 exclusive selection lines 38 extend from the decoder 40. Dimension selection is performed using x, yr sii selection gates 34.3 provided for each sense amplifier.
6.

As in Figure 7, there are three types of dimension selection (x.

y, s), it is necessary to prepare three systems for each sense amplifier (focus line), and this point does not change in FIG. However, in Fig. 1, the selection circuit for each system is one Noah gate 72X, 72Y, etc., and as is clear from the comparison with Fig. 6, it has been greatly simplified (about 1/3). and is about the same as in Fig. 7. The number of selected lines is significantly reduced compared to FIG. 7.

Also, in FIG. 1, as many systems as the number of selected dimensions are required for each sense amplifier, and one system requires a spacing of about one bit line, so that the spacing between bit lines becomes large at this point. This point can be improved as follows. In other words, the data in Figure 4 (16 x 16 = 256 bits) is stored in one word line.
However, each bit is stored discretely every three bits (three memory cells) in this example. For example, the first 16 bits in the X direction (0th segment) are shown in Figure 5.
In Figure 7, etc., the focus line is 0.1, 2.・Old...15,
The next 16 bits in the X direction (first segment) are bit lines 16, 17, 18, . ...31 (the same applies hereafter), but in the present invention, the 0th segment is set to 0 of the bit line.
．． 4,8. ...60, the first segment is connected to bit lines 64, 68, 72 .・・・・・・Place it at 123 (the same applies hereafter). Therefore, the number of bit lines in the memory cell is 256.
X4=1024. If data is placed in each of the three empty bits in the same way, four sheets of two-dimensional data (16x16 bits) as shown in FIG. 4 will be stored on one word line. 2) Co and C+ are bits for selecting any one of these four cards, and 32 is a decoder that produces the selected output. The number of sense amplifiers is the same as that of bit lines, therefore 1
024 pieces are provided, but here it is 256 pieces x 4,
Subscripts A, B, C, and D are attached to each group.

Now, if we set the 2 bits co and C+ to 00, for example, and select group A, gates 72A, 73A, . . . open, and sense amplifiers 5A72A, 5A73A, . . .
・is the output line L72. L73. It is connected to...

Assuming that the data on the word line is as above, 5AT2A
The output of is that of the 8th bit of the 4th group in the X direction,
Segment selection bin given to decoder 40) Bo=
If B3 indicates 4, the decoder sets the output cuff to L, and if dimension selection signal i is L, NOR gate 72X produces an H level output and opens transfer gate 72x. Therefore, the 5A72A(7) output is provided to data bus 8.1. Sense amplifier SA? The output of 3A is the 4th group 9 in the X direction.
This is opened by the output line L73 and the output of the NOR gate 73X which outputs the H level by the output 4=L of the encoder 40 (through the transfer gate 73x and the data bus 9°9). given to.

The same applies to the others, and the same applies when the decoder 32 selects groups B, C, and D.

In other words, each data of the data group (16 x 16 bits mentioned above) to be multidimensionally selected is stored in the memory cells on the word line at intervals corresponding to the number of dimensions, and the other data are stored in the empty memory cells. If each data in the multidimensional selection target data group is also stored discretely so that the data of the same data group appears discretely on the bit line group, a space is created to accommodate the selection circuit of each dimension, and the bit line spacing is This eliminates the problem of not being able to accommodate the selection system of each dimension unless it is made large. In addition, by similarly filling data of other data groups into empty memory cells in a discrete arrangement and selectively outputting them by the decoder 32, waste can be eliminated and the degree of integration can be improved.

Note that a latch circuit is provided, and the data read by selecting one word line is taken into this launch circuit, and then sent to the decoder 32.
The group selection may be performed by the decoder 40, the dimension and segment selection may be performed by the selection circuit, etc.

Of course, the number of bits of the data group stored on each word line can be increased or decreased as appropriate, and the number of selected dimensions can also be increased or decreased.

The method of arranging data on the word line can also be changed as appropriate, such as arranging Y-direction data or S-plane data in order instead of arranging X-direction data in order as described above. In addition, in FIG. 1, since the L selection method is used, the output of the decoder 40 and the dimension selection signal x+ y+'' are L active, gate?
2X, 72Y, . . . are NOR gates, but they may also be H active or AND gates.

Some selection gates 34 have the same input. For example 72
Since X and 73X, and 723 and 73S are powered by the same person, only one gate is required, and the output thereof can be guided to each transfer gate. This is shown in Figure 2. When 16 bits in the X direction are arranged in order on the word line, the sense amplifier SAo
The input of the NOR gate to ``-3 AI 5 is the same (output O of the decoder 40), and can be represented by the gate . The gate is an AND gate.Four surface selection gates each have the same input, so they are represented by AND gates O8, IS, 23, and 3S.Since there are no Y selection gates with the same input, they are provided individually. .OY.

IY,...FY are the selection gates.

In FIG. 2, the A group, B group, . . . are omitted, and they are simply shown as SAO, SAI, . LO,L
l.

... is L72. Output line equivalent to L73 etc.
Transfer gates corresponding to 72x, 72y, . . . are attached ahead of this, and each gate is ox, oy, os.

It is opened and closed by the output of... Although only the O-th segment is shown in FIG. 2, the same applies to the other segments. When arranging bits in the Y direction on the word line in order, use
, Y are exchanged, and the Y selection gate is commonly used for the segment.

〔Effect of the invention〕

As explained above, according to the present invention, multi-dimensional access is possible, and there is no need to take up decoder space or select too many lines, providing a memory suitable for image processing, etc. can do.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a partial modification of Fig. 1, Figs. 3 and 4 are explanatory diagrams of multidimensional data, Fig. 5 6 is a circuit diagram of the main part showing an example of multidimensional access, and FIG. 6 is a circuit diagram of the decoder section of FIG. 5.
FIG. 7 is a circuit diagram showing another example of multidimensional access, and FIG. 8 is a block diagram showing the overall configuration of FIG. 7. In FIG. 1, 20 is a data bus, 16 is a selection circuit, 38 is a selection line, 34 is a selection gate, 72X, 72Y, etc.
・ is each gate, 36 is a transfer gate, 72x
, 72y, . . . are respective gates thereof, and 12 is a sense amplifier group.

Claims (4)

[Claims] (1) Data bus (20) capable of multiple bit parallel output
and a cell array (10) in which a multi-bit data group consisting of a plurality of segments is written into a memory cell on one word line, with the plurality of bits as one segment, and a cell array (10) that receives segment addresses (B_0 to B_3) and produces its decoded output. A decoder (40), a selection line (38) receiving the output of the decoder, a dimension selection signal (x, y, s) line, a transfer gate (36) connecting the bit line of the cell array to the corresponding line of the data bus, and a selection circuit (16) having a selection gate (34) that receives the decoder output and the dimension selection signal and generates an output for turning on and off the transfer gate;
, and a multidimensional access memory. (2) Gate circuit that turns on and off the transfer gate (
34) is characterized in that those having the same input are grouped into one, and the output of the common gate (OX, OS,...) is guided to each of the corresponding transfer gates. A multidimensional access memory according to claim 1. (3) Data bus (20) capable of multiple-bit parallel output
Then, a multi-bit data group consisting of the plural segments is written into the memory cells on one word line in a discrete manner according to the number of selected dimensions, with the plural bits as one segment, and other multi-bit data are written into the vacant memory cells. A cell array (10) in which a data group is similarly written discretely, and each sense amplifier (SA72A, SA72B, ...) connected to each bit line of the cell array are connected to each bit in the data group. Each output line (L72, L73,...
), a decoder circuit (32, 72A, . . . ) is connected according to the group selection bits (C_0, C_1), and a decoder (40 ), a selection line (38) that receives the output of the decoder (40), a dimension selection signal line (x, y, s), a transfer gate (36) that connects the output line to the corresponding line of the data bus, and A multidimensional access memory comprising: a selection circuit (16) having a gate circuit (34) that receives a decoder output and a dimension selection signal and generates an output for turning on and off the transfer gate. (4) Gate circuit that turns on and off the transfer gate (
34) means that those with the same input are grouped into one, and the output of the common gate (OX, OS,...) is commonly led to each of the corresponding transfer gates. A multidimensional access memory according to claim 3, characterized in that: