JPS63140370A - Address computing element - Google Patents

Abstract

PURPOSE:To improve an execution efficiency by reducing an address arithmetic operation to invalid data when the invalid data is successive. CONSTITUTION:A value obtained by multiplying a distance between elements by one - three is added once by inputting the distance between the elements shifted by one bit leftward to the residual input of a three input adder 1. When more than three invalid data is successive, selection signals 109 - 111 to select an address register output 113, an output 115 of one bit leftward shift circuit 5 and a distance 105 between the elements respectively are sent to selection circuits 2 - 4 and a memory access request 114 is not sent to a memory access controller. The three input adder 1 inputs the outputs 106 - 108 of the selection circuits 2 - 4 to feed an addition output 112 to an address register 6 and the memory access controller.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an address calculator for a data processing device, and more particularly, to an address calculator for a data processing device, which is equipped with a three-input adder and can add a base address, an index value, and a displacement at the same time. Regarding address calculator.

Conventional technical data processing equipment decomposes a matrix into multiple vectors for processing, but matrices handled by data processing equipment generally do not store valid data in all elements, but are valid only in a small number of elements. data is stored, other elements are 110
It is often jl. This tendency becomes stronger as the matrix gets larger. Therefore, a vector mask is provided for each vector element, recording information as to whether valid data is stored, and memory access operations are not performed for elements storing invalid data.

Conventionally, this type of address calculator finds the address of the first element of a vector from the base address, index value, and displacement, stores the address of the previous element in an address register, and calculates the output and the distance between the elements! (distance between adjacent vector elements) to find the address of the next vector element. and,
Whether memory access is actually performed or not depends on the value of the vector mask.

Problems to be Solved by the Invention The conventional address arithmetic unit described above performs address arithmetic operations even on invalid data, so when invalid data is continuous, an additional arithmetic operation is required for the number of invalid data. This has the disadvantage of lower execution efficiency. It is possible to improve execution efficiency if the value obtained by multiplying the distance between elements by the number of consecutive invalid data can be added at once, but this requires a dedicated multiplier, and a significant increase in hardware is unavoidable. .

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology. Therefore, an object of the present invention is to replace the 3-input adder with 2-input addition in the address operation of the second and subsequent elements of a vector. Note that it is only used as a container, and by inputting the inter-element distance shifted to the left by 1 bit as the remaining input, it is possible to add values that are 1 to 3 times the inter-element distance at once. , reduce address calculation operations for invalid data when invalid data is continuous,
An object of the present invention is to provide a new address calculator that can improve execution efficiency.

Means for Solving the Problems In order to achieve the above object, an address arithmetic unit according to the present invention includes an address register that stores the result of address arithmetic, and a first selection circuit that can select the output of the address register. a second selection circuit capable of selecting a value obtained by shifting data indicating the distance between elements to the left by 1 bit and a fixed value of 0; and a third selection circuit capable of selecting data indicating the distance between the elements. an arithmetic resource determination circuit that generates a selection signal to be supplied to the first, second, and third selection circuits from the microinstruction decode signal and the value of the vector mask; and outputs of the first, second, and third selection circuits. and a three-input adder that receives as input.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Referring to FIG. 1, one embodiment of the present invention includes a three-input adder 1, a selection circuit 2.3.4, a 1-bit left shift circuit 5, an address register 6, and an arithmetic resource determination circuit 7.
It consists of:

When the microinstruction decode signal 116 indicates a normal data access microinstruction, the arithmetic resource determination circuit 7 selects the base address 101, index value 102, and displacement 104 for the selection circuit 2.3.4, respectively. In addition to sending selection signals 109, 110, and 111 such that The 3-input adder 1 has a selection circuit 2
, 3.4 and sends the addition output 112 to the address register 6 and the memory access control device.

When the microinstruction decode signal 116 indicates a microinstruction that accesses the head element of the vector, the arithmetic resource determination circuit 7 sends the base address 101, index value 102, and displacement to the 1 selection circuit 2.3.4, respectively. Selection signal 109.110, lI to select 104
In addition to sending I, to the memory access control device,
Looking at the vector mask value 117, if valid data is stored in the first element, a memory access request 114 is sent, and if invalid data is stored, no memory access request is sent. The three-input adder 1 includes selection circuits 2.3.
The outputs 106, 107, and 108 of 4 are input, and the addition output 112 is sent to the address register 6 and the memory access control device.

When the microinstruction decode signal 116 indicates a microinstruction that accesses the second or subsequent elements of the vector, the arithmetic resource determination circuit 7 determines the vector mask value 117.
If the element is valid data, the address register output 1 is sent to the selection circuit 2.3.4 respectively.
13. Selection signals 109, 110, and 111 are sent to select the fixed value 0103 and the inter-element distance 105, and a memory access request 114 is sent to the memory access control device. If that element is invalid data but the next element is valid, a 1-bit left shift circuit 5 inputs the address register output 113 and the inter-element distance 105, respectively, to the selection circuit 2.3.4. Output 115, fixed value 01
Selection signal 109, 110.111 that selects 03
At the same time, a memory access request 114 is sent to the memory access control device. If that element and the next element are invalid data, but the next element is valid, the arithmetic resource determination circuit 7 outputs 113.1 bits of address register to the selection circuit 2.3.4, respectively. Selection signals 109, 110, and 111 for selecting the output 115 of the left shift circuit 5 and the inter-element distance 105 are sent, and a memory access request 114 is sent to the memory access control device. If three or more pieces of invalid data are consecutive from the element, the address register output 113.1 bit left shift circuit 5 output 115 is sent to the selection circuit 2.3.4, respectively.
, a selection signal 109 . to select the inter-element distance 105 .
110 and 111, and does not send a memory access request 114 to the memory access control device. 3-input adder 1 outputs 106.107.1 of selection circuit 2.3.4
08, and add output 112 to address register 6.
and the memory access controller.

Note that if the output 115 of the 1-bit left shift circuit 5 can be input to the selection circuit 4, it is possible to add up to a value that is 1 to 4 times the inter-element distance, and a 2-bit left shift circuit can also be added. If the output can be input to the selection circuit 3.4, it is possible to create a configuration in which up to a value multiplied by 1 to 6 can be added.

As described in detail, according to the present invention, the distance between elements is 1 to 1.
By making it possible to add the tripled value at once and reducing the number of address calculation operations for invalid data when the invalid data is continuous, it is possible to obtain the effect of improving execution efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1,,. 3-input adder, 200. first selection circuit, 38
1. second selection circuit, 410. third selection circuit, 5. ,
．． 1-bit left shift circuit, 6. ,. address register, 700. Computing resource determination circuit, 1
01. , , base address, 102. , , Indesk value, 103. , , fixed value 01104. ,
, Displacement, 105, , Inter-element distance, 106. ,
, the output of the first selection circuit, 107. , , the output of the second selection circuit, 108. . , the output of the third selection circuit, 109. , , selection signal to the first selection circuit, 110. , , selection signal to the second selection circuit, 111. , , selection signal to third selection circuit, 112. , , addition output, 114. ', , address register output, 115. , , 1-bit left shift circuit output, 116. , , Microinstruction decode signal, 117°8. vector mask value

Claims (1)

[Claims] an address register that stores the result of the address operation; a first selection circuit that can select the output of the address register; and a first selection circuit that can select between a value obtained by shifting data indicating the inter-element distance to the left by 1 bit and a fixed value of 0. a second selection circuit, a third selection circuit capable of selecting data indicating the distance between elements, and a selection signal supplied to the first, second and third selection circuits from the microinstruction decode signal and the value of the vector mask. 1. An address arithmetic unit comprising: an arithmetic resource determination circuit that generates an arithmetic resource determination circuit; and a three-input adder that receives the outputs of the first, second, and third selection circuits as inputs.