JPS63139407A - Negative feedback type crystal oscillator using complementary metallic oxide film semiconductor - Google Patents

Negative feedback type crystal oscillator using complementary metallic oxide film semiconductor

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Publication number
JPS63139407A
JPS63139407A JP61241597A JP24159786A JPS63139407A JP S63139407 A JPS63139407 A JP S63139407A JP 61241597 A JP61241597 A JP 61241597A JP 24159786 A JP24159786 A JP 24159786A JP S63139407 A JPS63139407 A JP S63139407A
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JP
Japan
Prior art keywords
source
negative feedback
gate
drain
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61241597A
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Japanese (ja)
Inventor
Saburou Chiba
千葉 作富郎
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Individual
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Individual
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Priority to JP61241597A priority Critical patent/JPS63139407A/en
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  • Oscillators With Electromechanical Resonators (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To improve an oscillation frequency fluctuation ratio characteristic to the fluctuation of a power source voltage and the change of an ambient temperature by inserting and connecting a resistance into respective sources of a metallic oxide film semiconductor electric field effect transistor MOS FET, forming the negative feedback circuit of a serial crossflow, inserting the resistance between the gate and the drain of respective stages and forming a parallel negative feedback circuit. CONSTITUTION:In a complementary metallic oxide film semiconductor (CMOS) single stage amplifier, a resistance (R1) is inserted between a metallic oxide semiconductor electric field effect transistor (MOS FET)T 1 source and a ground, a resistance (R2) is inserted between a T2 source and a resistance (R2) and the negative feedback circuit of the serial crossflow is formed. The fluctuation of the parameter of FETT1 and T2 is made smaller, and the bias between the gate and the source is also made stable. Further, a resistance (R3) is inserted from the drain to the gate, the negative feedback of the parallel crossflow is executed and the bias between the gate and the source is made stable. Further, a frequency determining circuit (C, C1 crystal oscillator circuit) is positively fed back from the drain to the gate. At this time, a capacity (C) is made larger as much as possible, determined to the extent of a=C/C1=5-11, a necessary amplification degree is made smaller, and an excess amplification degree is turned to the negative feedback. For this reason, the oscillation frequency fluctuation ratio characteristic is improved.

Description

【発明の詳細な説明】 腕時計用等の水晶発振器の発振周波数は3.2768M
H2が多く用いられているが、電源電圧1,5■の約3
0%低下に対してlppm程度の発振周波数変動率が認
められる、図1に示す回路が従来から用いられているも
のである。容ffi (C)の値が比較的小さく、a=
C/c1の値が1〜4程度であり、従って所要増幅度が
大きくなって、負帰還ずべき余裕増幅度が少ない、更に
T1とT2の各ソースに直列形負帰還を実施していない
為に、TI 、T2の各金属酸化膜半導体電界効果トラ
ンジスタ(MOS  FET>のパラメータ変動率が大
きくなり、電源電圧の変動や周囲温度の変化に対しての
発振周波数変動率特性が悪いのである。
[Detailed description of the invention] The oscillation frequency of a crystal oscillator for wristwatches, etc. is 3.2768M.
H2 is often used, but the power supply voltage is about 3
The circuit shown in FIG. 1, in which an oscillation frequency fluctuation rate of about 1 ppm is observed for a 0% decrease, has been conventionally used. The value of capacity ffi (C) is relatively small, and a=
The value of C/c1 is about 1 to 4, so the required amplification is large, and there is little margin for negative feedback. Furthermore, series negative feedback is not implemented for each source of T1 and T2. Moreover, the parameter fluctuation rate of each metal oxide semiconductor field effect transistor (MOSFET) of TI and T2 becomes large, and the oscillation frequency fluctuation rate characteristics with respect to fluctuations in power supply voltage and changes in ambient temperature are poor.

また、図2に示すのは、補償用水晶による相補性金属酸
化膜半導体(CMOS)水晶発振器のりアクタンス安定
化法による回路である。この1′J性を図3に示す。
Also shown in FIG. 2 is a circuit using a complementary metal oxide semiconductor (CMOS) crystal oscillator actance stabilization method using a compensation crystal. This 1'J property is shown in FIG.

電源電圧の違いがあるが、電圧の約30%低下に対して
約1Dpm〜0.5ppmの発振周波数変動率特性を示
しあまり良好でない。これは容ffi (C)の値が比
較的小さく、しかもa=C/C1=1〜2程度であり、
従って所要増幅度が大きくなり負帰還すべき余裕増幅面
分が少ない、更にT1とT2の各ソースに直列形負帰還
を施していない為に、T1、T2の金属酸化膜半導体電
界効果トランジスタ(MOS  FET)のパラメータ
変動率が大きくなり、電源電圧の変動や周囲温度の変化
に対しての発[辰周波数変動率特性が悪いのである。更
に補償用水晶1ヶを余i1に使用する欠点を有する。ま
たリアクタンス安定化法は針線上はトランジスタパラメ
ータが発振周波数に影響しないと出るが、同時に要請さ
れる安定化条件を剖算値通りに実際回路で一致させるの
は困難なので実際回路での発1辰周波数変動率が悪いの
である。図3はそれを示す。すなわちCと01の値を色
々変えて実験しているが、電源電圧の30%低下に対す
る発振周波数変動率がIpI)m〜0.5ppmと大幅
に変化しているのが実験回路での困難性を明示している
のである。更にRglとR(+2とによりゲートバイア
スを負帰還善しで施している欠点を有する。
Although there is a difference in power supply voltage, the oscillation frequency fluctuation rate characteristic is about 1 Dpm to 0.5 ppm for a voltage drop of about 30%, which is not very good. This means that the value of ffi (C) is relatively small, and moreover, a=C/C1=1 to 2,
Therefore, the required degree of amplification increases, and the margin for negative feedback is small.Furthermore, since series negative feedback is not applied to the sources of T1 and T2, the metal oxide semiconductor field effect transistors (MOS) of T1 and T2 are This increases the parameter fluctuation rate of the FET (FET), resulting in poor frequency fluctuation characteristics with respect to fluctuations in power supply voltage and changes in ambient temperature. Furthermore, it has the disadvantage that one compensating crystal is used for the remainder i1. In addition, although the reactance stabilization method shows that the transistor parameters do not affect the oscillation frequency, it is difficult to match the required stabilization conditions to the calculated values in the actual circuit, so the oscillation frequency in the actual circuit is difficult. The frequency fluctuation rate is bad. Figure 3 shows this. In other words, we are experimenting with various values of C and 01, but the difficulty in the experimental circuit is that the oscillation frequency fluctuation rate for a 30% drop in power supply voltage changes significantly from IpI)m to 0.5 ppm. It clearly shows that. Furthermore, it has the disadvantage that the gate bias is applied with negative feedback by Rgl and R(+2).

次いで本発明の構成とその効果とについて述べる。Next, the configuration of the present invention and its effects will be described.

図4に示すような3段形相補性金属酸化膜半導体(0M
C3>増幅器において、(既製品(市販品)は出廻って
いない、しかしながら現在の1.C,製造技術よりみて
容易に製作可能な回路である。)金属酸化膜半導体電界
効果トランジスタ(MC3FET>T1、 T2. T
3. T4. T5. T6.の各ソース(Sl、G2
.G3゜34、35. G6)に抵抗(R1,R2,R
3,R4,R5,R6)を挿入して直列形(電流形)の
直交流の負帰還を施すと共に、各段のゲート〜ドレーン
間に(D1→G1、D2→G2 、D3→G3 、D3
→G1間)抵抗(R7゜R8,R9,R10)を挿入し
て並列形(電圧形)の直交流の負帰還を施して、金属酸
化膜半導体電界効果トランジスタ(MC3FET)の諸
パラメータの変動分を小さくしている、更にT5ソース
(G5)よりT1ソース(S1)へ抵抗(R11)を、
またT6ソース(G6)、!:すT2ソース(G2)へ
抵抗(R12)を挿入して接続し、更にT6ソース(G
6)よりT1ソース(S1)へ抵抗(R13)を、また
T5ソース(G5)よりT2ソース(G2)へ抵抗(R
14)を挿入して、段間の直交流の負帰還回路を構成し
て相補性金属酸化膜半導体<0MC3>増幅部の諸パラ
メータ変動率を極めて小さく抑制している。更に周波数
決定回路の容!(C)をできるだけ大きくし、しかもa
=C/Cl−5〜11程度に決めて所要増幅度を小ざく
しで、余裕増幅度を負帰還に廻して一層発振周波数安定
度を増している。
A three-stage complementary metal oxide semiconductor (0M
In the C3> amplifier, (there are no off-the-shelf products (commercial products) on the market, however, it is a circuit that can be easily manufactured considering the current 1.C manufacturing technology.) Metal oxide film semiconductor field effect transistor (MC3FET>T1 , T2.T
3. T4. T5. T6. Each source (Sl, G2
.. G3゜34, 35. G6) and resistors (R1, R2, R
3, R4, R5, R6) to perform series type (current type) cross-current negative feedback, and also insert (D1→G1, D2→G2, D3→G3, D3) between the gate and drain of each stage.
→G1) Resistors (R7゜R8, R9, R10) are inserted to provide parallel type (voltage type) cross-current negative feedback to compensate for fluctuations in various parameters of the metal oxide semiconductor field effect transistor (MC3FET). In addition, a resistor (R11) is connected from the T5 source (G5) to the T1 source (S1).
Also T6 sauce (G6)! : Insert and connect the resistor (R12) to the T2 source (G2), and then connect it to the T6 source (G2).
6) from the T1 source (S1), and from the T5 source (G5) to the T2 source (G2).
14) is inserted to form a negative feedback circuit for cross-current flow between stages, thereby suppressing the fluctuation rate of various parameters of the complementary metal oxide film semiconductor <0MC3> amplifier section to an extremely low level. Furthermore, the capacity of the frequency determining circuit! Make (C) as large as possible, and a
=C/Cl-5 to about 11, the required amplification degree is reduced, and the margin amplification degree is turned to negative feedback to further increase the oscillation frequency stability.

従って電源電圧や周囲温度の変化に対する発振周波数変
動率特性は後述の如く、従来発表されている回路方式よ
りもかムリの良妊升It y−D 、sのζ′$3.な
お図4に示すようにドレーン(D3)よりゲート(G1
)へ容量(C,CI)と水晶振動子から成る発振周波数
決定回路を正帰還させている。
Therefore, as will be described later, the oscillation frequency fluctuation rate characteristics with respect to changes in power supply voltage and ambient temperature are much better than conventional circuit systems. Note that as shown in Figure 4, the gate (G1) is lower than the drain (D3).
) is positively fed back to the oscillation frequency determining circuit consisting of capacitors (C, CI) and a crystal resonator.

次いで本発明の具体的回路例として図5に示すように相
補性金属酸化膜半導体(0MC8)1段増幅器において
、(既製品(市販品)が有り例えばMC14000UB
ヤMC74HCUO4やMC14069UBなどである
)T1ソースとアース間に抵抗(R1)を挿入し、また
T2ソースと電源間に抵抗(R2)挿入して、直列形の
直交流の負帰還回路を形成して、金属酸化膜半導体電界
効果トランジスタ(MC8FET>TI とT2 (7
)パラメータの変動を小さくすると共に、ゲートとソー
ス間のバイアスをも安定化している。更にドレーンより
ゲートへ抵抗(R3)を挿入して並列形の直交流の負帰
還を施して、ゲートとソース間のバイアスを安定化して
いる。更に周波数決定回路(C,CI水品振動子回路)
をドレーンよりゲートへ正帰還させている。この際に容
ffi (C)をできるだけ大きクシ、シかもa=c/
c1=5〜11程度に決めて所要増幅度を小さくして、
余裕増幅度を負帰還に廻しているので、発振周波数変動
率特性が良好となる。従って図6に示すように、電源電
圧 ±ΔDD=±30% の変化に対してΔflf合±
5.5X 1O−8= 0゜055ppm程度であり(
電源電圧は従来のものに比べて倍変化させている)、周
囲温度の変化に対しては、ΔTa=−5〜55℃変化に
対してΔf/f与±1.5X10−7=±0.15 p
pm程度である。(但しCC1水晶は室温で一定に保っ
て実験している。これはTI T21−ランジスタの入
出力抵抗、位相角や伝達コンダクタンス等の影響をどの
程度減少させているかを観察することに重点をおいたた
めである。)電源電圧特性は従来のものと比較して約1
0倍Δf/f’特性が向上している。
Next, as a specific circuit example of the present invention, as shown in FIG.
(MC74HCUO4, MC14069UB, etc.) Insert a resistor (R1) between the T1 source and ground, and also insert a resistor (R2) between the T2 source and the power supply to form a series cross-current negative feedback circuit. , metal oxide semiconductor field effect transistor (MC8FET>TI and T2 (7
) In addition to reducing parameter fluctuations, the bias between the gate and source is also stabilized. Furthermore, a resistor (R3) is inserted from the drain to the gate to provide parallel cross-current negative feedback to stabilize the bias between the gate and source. Furthermore, the frequency determination circuit (C, CI water resonator circuit)
positive feedback from the drain to the gate. At this time, make the comb (C) as large as possible, maybe a=c/
Decide c1=5 to 11 and reduce the required amplification,
Since the margin amplification is turned to negative feedback, the oscillation frequency fluctuation rate characteristics are improved. Therefore, as shown in Figure 6, the Δflf value ±
5.5X 1O-8 = about 0゜055ppm (
(The power supply voltage is doubled compared to the conventional one), and for changes in ambient temperature, Δf/f is ±1.5X10-7=±0. 15 p.
It is about pm. (However, the CC1 crystal was kept constant at room temperature during the experiment. This focused on observing how much the effects of the input/output resistance, phase angle, transfer conductance, etc. of the TI T21 transistor were reduced. ) The power supply voltage characteristics are approximately 1
The 0x Δf/f' characteristic is improved.

次いで、図7に示すような3段形相補性金属酸化膜半導
体(0MC3)増幅器において(既製品(市販品)が有
り、例えばMC14000B等) T1、T3.T5.
の共通のソース(A点)とアース間に抵抗(R1)を挿
入接続し、またT2. T4.丁6.の共通ソース(B
点)と電源間に抵抗(R2)を挿入して、直り11形(
電流形)の直交流の負帰還回路を形成し、またドレーン
(D3)よりゲート(G1)へ抵抗(R3)を挿入して
並列形(電圧形)の直交流の負帰還を施して相補性金属
酸化膜半導体(0MC3>増幅器の諸パラメータの変動
分を小さく抑制している。(市販品なので、DI −G
2とD2−G3とは直結になっている。) 更にドレーン(D3)よりゲート(G1)へ容量(C。
Next, in a three-stage complementary metal oxide semiconductor (0MC3) amplifier as shown in FIG. T5.
A resistor (R1) is inserted and connected between the common source (point A) of T2. T4. Ding 6. common source (B
Insert a resistor (R2) between the point) and the power supply to connect the straight type 11 (
Complementarity is achieved by forming a cross-current negative feedback circuit (current type), and inserting a resistor (R3) from the drain (D3) to the gate (G1) to provide parallel type (voltage type) cross-current negative feedback. Metal oxide film semiconductor (0MC3> Variations in various parameters of the amplifier are suppressed to a small level. (Since it is a commercially available product, DI-G
2 and D2-G3 are directly connected. ) Furthermore, capacitance (C) is added from the drain (D3) to the gate (G1).

CI )と水晶振動子からなる周波数決定回路を正帰還
させている。この場合に容量<cニドレーン側の容量の
こと)をできるだけ大きくして(Cを大きくすると発振
が困難になる) 、a=c/cL= 5〜11程度にと
っているので、所要増幅度が小さくなり、余裕増幅度を
負帰還に廻すことができるので発娠周波数変動率特性は
比較的良好となっている。図8にその特性を示す。
A frequency determining circuit consisting of CI) and a crystal oscillator is subjected to positive feedback. In this case, the capacitance <c (the capacitance on the side of the drain) is made as large as possible (increasing C makes it difficult to oscillate), and a=c/cL=about 5 to 11, so the required amplification is small. Since the margin amplification can be used for negative feedback, the starting frequency fluctuation rate characteristics are relatively good. Figure 8 shows its characteristics.

電源電圧の士乙Vxzn =土304壷化1;村L7Δ
r/f:=±3.5x 1O−8=±o、o3sppm
程度と小ざく、従来のものと比較して約10倍強良好と
なっている。
Power supply voltage value Vxzn = soil 304 pot 1; village L7Δ
r/f:=±3.5x 1O-8=±o, o3sppm
Although it is only slightly rough, it is about 10 times better than the conventional one.

周囲温度の変化にに対しては ΔTa=−5〜+55℃の変化に対してはΔf/fか±
5.5X 1O−8=±0.055ppm程度と小ざく
なっている。
For changes in ambient temperature, Δf/f or ± for changes in ΔTa = -5 to +55°C.
It is as small as 5.5X 1O-8=±0.055ppm.

更に本発明の趣旨をこれ迄定性的に述べてきたが、−歩
進んで定量的かつ理論的に説明することとする。すなわ
ち相補性金属酸化膜半導体(CMOS>1設地幅器と、
容1(C,C1)と水晶振動子からなる発振周波数決定
回路と、相補性金属酸化膜半導体(CMOS>よりなる
帰還形水晶発振回路において、(1算の手順として、ま
ず相補性金属酸化膜半導体(0MO5)増幅器の特性を
解析し、更に周波数決定回路を挿入した場合の発振周波
数決定条件式を導く。これはかなり長い計算なので要点
のみを記して細部は割愛する。
Furthermore, although the gist of the present invention has been described qualitatively up to now, it will now be explained quantitatively and theoretically. That is, a complementary metal oxide semiconductor (CMOS>1 device),
In the oscillation frequency determination circuit consisting of a capacitor 1 (C, C1) and a crystal oscillator, and the feedback type crystal oscillation circuit consisting of a complementary metal oxide semiconductor (CMOS), The characteristics of a semiconductor (0MO5) amplifier are analyzed, and the conditional expression for determining the oscillation frequency when a frequency determining circuit is further inserted is derived.This is a fairly long calculation, so only the main points will be described and the details will be omitted.

ここで発振周波数決定条件式は−・般にAω5−Bω4
+Cω3−Dω2+Eω−F=o −417なる5次方
程式で表わされて、一般的には解析は不可能である。し
かしながら実際回路定数をA、8.C。
Here, the conditional expression for determining the oscillation frequency is - generally Aω5-Bω4
It is expressed by a quintic equation: +Cω3-Dω2+Eω-F=o-417, and analysis is generally impossible. However, the actual circuit constants are A, 8. C.

D、E、F、に代入することによりABCDEFは既知
数となるので、コンピュータで解析が可能となり、未知
数のω(fo)を求めることができる。
By substituting D, E, and F, ABCDEF becomes a known number, so it can be analyzed by a computer and the unknown number ω(fo) can be found.

(ω=2πfO) 故に各電源電圧値でのABCDEFを求めて(1)式に
代入して計算し、グラフに描いて理論値乙なし、一方同
一グラフ上に実測値を描くことにJ:す、発振周波数変
動率特性が明らかになる。すなわら、理論値と実測値と
は同桁で同傾向の曲線を示して変動していることが判明
した。すなわち理論値と実測値とが程良い一致性を示し
たのである。かくてコンビュークシSニレ−ジョンによ
り本発明回路が秀れた周波数安定度を有することが実験
的にも、理論的にも明らかとなったのである。
(ω = 2πfO) Therefore, ABCDEF at each power supply voltage value is calculated by substituting it into equation (1), and it is plotted on a graph without the theoretical value.On the other hand, the actual value is plotted on the same graph. , the oscillation frequency fluctuation rate characteristics become clear. In other words, it was found that the theoretical value and the measured value fluctuated at the same order of magnitude and showed the same trend curve. In other words, the theoretical value and the measured value showed good agreement. In this way, it has become clear both experimentally and theoretically that the circuit of the present invention has excellent frequency stability due to the Conbuxis Snillion.

以下に回路解析の概要を記す。The outline of the circuit analysis is described below.

図9は相補性金属酸化膜半導体(CMOS>帰還形の伝
達コンダクタンスの絶対値とその位相角θ とドレーン
抵抗G Qz である。図10は図9の等価回路図であ
り、抵抗(R3)で負帰還を施し、更に抵抗(R1) 
(R2)で負帰還を形成し、容量(C,CI)と水晶振
動子(LX CX RX )を正帰還している。図11
は相補性金属酸化膜半導体(CMOS>のT1金属酸化
膜半導体電界効果トランジスタ(MOS  FET>1
段の等価回路図である。ここで、 T4=Q  −12) V3 ・ Tz  RH”ノ ごミz°′ ぐコ2・・ノη’−11111!F二カッ!1つ 2Z
り2シ1υかヒ妾鱒チtea  a’(=0   イ「
28t:   1’l16+b  R’(t7>t+?
λ(9)(2u)   E  r1゛)(+20J馨米
 のキ礒tUど功ヰ1S竹j。
Figure 9 shows the absolute value of the transfer conductance of a complementary metal oxide semiconductor (CMOS>feedback type), its phase angle θ, and the drain resistance GQz. Figure 10 is an equivalent circuit diagram of Figure 9, and the resistance (R3) Apply negative feedback and further resistor (R1)
(R2) forms a negative feedback, and the capacitance (C, CI) and the crystal resonator (LX CX RX ) are subjected to positive feedback. Figure 11
is a complementary metal oxide semiconductor (CMOS) T1 metal oxide semiconductor field effect transistor (MOS FET)
FIG. 3 is an equivalent circuit diagram of a stage. Here, T4=Q -12) V3 ・ Tz RH "NOGOMIZ°'GUKO2...ノη'-11111! F Two Kats! One 2Z
ri2shi1υkahi concubine trout tea a'(=0 i'
28t: 1'l16+b R'(t7>t+?
λ (9) (2u) E r1゛) (+20J Kaorimai's Kisho tU Dokki 1S Bamboo j.

7゛み3゜7゛mi 3゜

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は相補性金属酸化膜半導体(CMOS)水晶発振
器の一例を示す回路図。 第2図は補償用水晶による相補性金属酸化膜半導体(C
MOS)水晶発振器の一例を示す回路図。 第3図は第2図示回路の電源電圧の変化に対する発振周
波数変動率特性を示す図。 第4図は本発明の一実施例を示す具体的回路図。 第5図は本発明の相異なる実施例を示す具体的回路図。 第6図は第5図に示した回路の電源電圧と周囲温度の変
化に対する発振周波数変動率特性を示す図。 第7図は本発明の相異なる実施例を示す具体的回路図。 第8図は第7図に示した回路の電源電圧と周囲温度の変
化に対する発振周波数変動率特性を示す図。 第9図は本発明の相異なる実施例を示す具体的回路の増
幅器の原理図。 第10図は本発明の相異なる実施例を示す具体的回路の
等価回路図。 第11図は本発明の相異なる実施例を示す具体的回路の
増幅器の金属酸化膜半導体電界効果トランジスタ(MO
S  FET)1ケの増幅器等価回路図。 第12図は本発明のブロック図。 第13図は本発明の相異なる実施例を示す具体的回路の
原理図。 特許出願人    千葉 作富部 。81δ2(ゾQpJ !  2   )  jj   ?   ia   /
/   /z1、r a       −+ L/DO
(V)寥121図 手続補正出(方式) %式% 1、事件の表示  昭和乙1年特許願第14.−(S’
17号半芥休水晶体T水春 3、補正をする者 事件との関係  特許出願人 住所(居所)
FIG. 1 is a circuit diagram showing an example of a complementary metal oxide semiconductor (CMOS) crystal oscillator. Figure 2 shows a complementary metal oxide semiconductor (C
1 is a circuit diagram showing an example of a MOS (MOS) crystal oscillator. FIG. 3 is a diagram showing the oscillation frequency fluctuation rate characteristics with respect to changes in power supply voltage of the circuit shown in the second diagram. FIG. 4 is a specific circuit diagram showing one embodiment of the present invention. FIG. 5 is a specific circuit diagram showing different embodiments of the present invention. FIG. 6 is a diagram showing the oscillation frequency fluctuation rate characteristics of the circuit shown in FIG. 5 with respect to changes in power supply voltage and ambient temperature. FIG. 7 is a specific circuit diagram showing different embodiments of the present invention. FIG. 8 is a diagram showing the oscillation frequency fluctuation rate characteristics with respect to changes in power supply voltage and ambient temperature of the circuit shown in FIG. 7. FIG. 9 is a diagram showing the principle of an amplifier of a concrete circuit showing different embodiments of the present invention. FIG. 10 is an equivalent circuit diagram of a specific circuit showing different embodiments of the present invention. FIG. 11 shows a specific circuit amplifier metal oxide semiconductor field effect transistor (MO2) showing different embodiments of the present invention.
S FET) 1 amplifier equivalent circuit diagram. FIG. 12 is a block diagram of the present invention. FIG. 13 is a principle diagram of a specific circuit showing different embodiments of the present invention. Patent applicant Sakutomi Chiba. 81δ2 (zoQpJ! 2) jj? ia /
/ /z1, r a −+ L/DO
(V) Issuance of amendment to figure 121 procedure (method) % formula % 1. Indication of case Showa Otsu 1 patent application No. 14. −(S'
No. 17 Hanbakukyu Crystalline Lens T Suishun 3, Relationship with the case of the person making the amendment Patent applicant address (residence)

Claims (3)

【特許請求の範囲】[Claims] (1)3段形相補性金属酸化膜半導体(CMOS)増幅
器(図4に示したようなもの)において、金属酸化膜半
導体電界効果トランジスタ(MOSFET)T1、T2
、T3、T4、T5、T6、の各ソース(Source
)(S1、S2、S3、S4、S5、S6、)に抵抗(
R1、R2、R3、R4、R5、R6、)を挿入接続し
て直列形の直交流の負帰還回路を形成すると共に各段の
ゲート(gate)とドレーン(drain)間に抵抗
(R7、R8、R9、R10)を挿入して(但しR10
はD3からGlへ接続する)並列形負帰還回路を形成し
更にT5ソース(S5)よりT1ソース(S1)へ抵抗
(R11)を挿入し、またT6ソース(S6)よりT2
ソース(S2)へ抵抗(R12)を挿入し、更にT6ソ
ース(S6)よりT1ソース(S1)へ抵抗(R13)
を挿入し、またT5ソース(S5)よりT2ソース(S
2)へ抵抗(R14)を挿入して、段間の直交流の負帰
還回路を構成すると共に、更に周波数決定回路の容量(
C)をできるだけ大きくして、しかもa=C/c1の値
を適当値にして、T5、T6のドレーン(D3)よりT
1、T2のゲート(G1)へ容量(C、C1)と水晶振
動子から成る発振周波数決定回路を正帰還させることを
特長とする負帰還形相補性金属酸化膜半導体(CMOS
)水晶発振器。
(1) In a three-stage complementary metal oxide semiconductor (CMOS) amplifier (as shown in Figure 4), metal oxide semiconductor field effect transistors (MOSFETs) T1, T2
, T3, T4, T5, T6,
) (S1, S2, S3, S4, S5, S6,) with resistance (
R1, R2, R3, R4, R5, R6,) are inserted and connected to form a series cross-current negative feedback circuit, and resistors (R7, R8) are connected between the gate and drain of each stage. , R9, R10) (however, R10
is connected from D3 to Gl), a parallel negative feedback circuit is formed, and a resistor (R11) is inserted from the T5 source (S5) to the T1 source (S1), and the T2 source is connected from the T6 source (S6).
Insert a resistor (R12) into the source (S2), and then insert a resistor (R13) from the T6 source (S6) to the T1 source (S1).
and also connect the T2 source (S5) to the T5 source (S5).
A resistor (R14) is inserted into 2) to configure a negative feedback circuit for cross-current flow between stages, and the capacitance (R14) of the frequency determining circuit is also
C) is made as large as possible, and the value of a=C/c1 is set to an appropriate value, so that T is smaller than the drain (D3) of T5 and T6.
1. Negative feedback complementary metal oxide semiconductor (CMOS) characterized by positive feedback of an oscillation frequency determining circuit consisting of capacitors (C, C1) and a crystal resonator to the gate (G1) of T2.
) crystal oscillator.
(2)1段形相補性金属酸化膜半導体(CMOS)増幅
器において(図5に示したようなもの)T1ソースとア
ース間に抵抗(R1)を挿入し、T2ソースと電源間に
抵抗(R2)を挿入して直交流の直列形負帰還回路を形
成し、ドレーンからゲートへ抵抗(R3)を接続して直
交流の並列形負帰還回路を形成すると共に、更に周波数
決定回路の容量(C)をなるべく大きくして、a=C/
c1を適当値にすると共に、容量(C、C1)と水晶振
動子からなる発振周波数決定回路をドレーンからゲート
へ正帰還させることを特長とする負帰還形相補性金属酸
化膜半導体(CMOS)水晶発振器。
(2) In a single-stage complementary metal oxide semiconductor (CMOS) amplifier (as shown in Figure 5), a resistor (R1) is inserted between the T1 source and the ground, and a resistor (R2) is inserted between the T2 source and the power supply. ) is inserted to form a cross-current series negative feedback circuit, and a resistor (R3) is connected from the drain to the gate to form a cross-current parallel negative feedback circuit. ) as large as possible, a=C/
Negative feedback complementary metal oxide semiconductor (CMOS) crystal characterized by setting c1 to an appropriate value and positively feeding back the oscillation frequency determining circuit consisting of capacitors (C, C1) and a crystal resonator from the drain to the gate. oscillator.
(3)3段形相補性金属酸化膜半導体(CMOS)増幅
器において(図7に示したようなもので、各ソースが共
通接続されて、各段のドレーンとゲートは直結されてい
るもの)T1、T3、T5、の共通ソース(A点)とア
ース間に抵抗(R1)を挿入し、またT2、T4、T6
、の共通ソース(B点)と電源間に抵抗(R2)を挿入
接続して直交流の直列形負帰還回路を形成し、ドレーン
からゲートへ抵抗(R_3)を接続し(D_3→G_1
)直交流の並列形負帰還回路を形成し、 更に周波数決定回路の容量(C)をなるべく大きくして
、a=C/C1を適当値に決めると共に、容量(C、C
1)と水晶振動子よりなる発振周波数決定回路をドレー
ンからゲートへ正帰還させることを、特長とする負帰還
形相補性金属酸化膜半導体(CMOS)水晶発振器。
(3) In a three-stage complementary metal oxide semiconductor (CMOS) amplifier (as shown in Figure 7, each source is commonly connected and the drain and gate of each stage are directly connected) T1 , T3, T5, a resistor (R1) is inserted between the common source (point A) and ground, and T2, T4, T6
A resistor (R2) is inserted and connected between the common source (point B) of , and the power supply to form a cross-current series negative feedback circuit, and a resistor (R_3) is connected from the drain to the gate (D_3 → G_1
) Form a cross-current parallel negative feedback circuit, further increase the capacitance (C) of the frequency determining circuit as much as possible, set a=C/C1 to an appropriate value, and set the capacitance (C, C
1) A negative feedback complementary metal oxide semiconductor (CMOS) crystal oscillator characterized by positive feedback of an oscillation frequency determining circuit consisting of a crystal resonator from the drain to the gate.
JP61241597A 1986-10-10 1986-10-10 Negative feedback type crystal oscillator using complementary metallic oxide film semiconductor Pending JPS63139407A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61241597A JPS63139407A (en) 1986-10-10 1986-10-10 Negative feedback type crystal oscillator using complementary metallic oxide film semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61241597A JPS63139407A (en) 1986-10-10 1986-10-10 Negative feedback type crystal oscillator using complementary metallic oxide film semiconductor

Publications (1)

Publication Number Publication Date
JPS63139407A true JPS63139407A (en) 1988-06-11

Family

ID=17076678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61241597A Pending JPS63139407A (en) 1986-10-10 1986-10-10 Negative feedback type crystal oscillator using complementary metallic oxide film semiconductor

Country Status (1)

Country Link
JP (1) JPS63139407A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5228344A (en) * 1975-08-25 1977-03-03 Honeywell Inc Device for placing object slide accurately and immovably on slide carrier tray of microscope
JPS5461447A (en) * 1977-10-26 1979-05-17 Toshiba Corp Crystal oscillation circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5228344A (en) * 1975-08-25 1977-03-03 Honeywell Inc Device for placing object slide accurately and immovably on slide carrier tray of microscope
JPS5461447A (en) * 1977-10-26 1979-05-17 Toshiba Corp Crystal oscillation circuit

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