JPS63136663A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63136663A JPS63136663A JP61281730A JP28173086A JPS63136663A JP S63136663 A JPS63136663 A JP S63136663A JP 61281730 A JP61281730 A JP 61281730A JP 28173086 A JP28173086 A JP 28173086A JP S63136663 A JPS63136663 A JP S63136663A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- source
- memory
- mos element
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 230000015654 memory Effects 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims description 2
- 230000006378 damage Effects 0.000 abstract description 11
- 230000007423 decrease Effects 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract description 6
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 9
- 230000002265 prevention Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000006187 pill Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はバイポーラＣＭＯＳメモリ半導体集積回路装置
等における情報破壊防止技術ならびにラッチアップ対策
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to information destruction prevention technology and latch-up countermeasures in bipolar CMOS memory semiconductor integrated circuit devices and the like.
バイポーラＣＭＯＳメモリについては、たとえばｌ５Ｓ
ＣＣ８６／ＴＨＵＲ８ＤＡＹ、 ＦＥＢＲＵＡＲＹ２０
．１９８６、Ｐ２１２に高密度バイポーラＣＭＯＳデバ
イスの断面図が示されている。このデバイスは１対のウ
ェル内のｐ−ＭＯＳ及びｎ−ＭＯＳとバイポーラｎｐｎ
）ランジスタがアイソレーシッン酸化膜によって分離さ
れて一つの基板表面に形成されたものである。For bipolar CMOS memory, for example l5S
CC86/THUR8DAY, FEBRUARY20
．． A cross-sectional view of a high-density bipolar CMOS device is shown in 1986, P212. This device consists of p-MOS and n-MOS in a pair of wells and bipolar npn
) The transistors are separated by an isolating oxide film and formed on the surface of one substrate.
本発明者はバイポーラＣＭＯＳメモリについて独自に開
発している。以下は、公知された技術ではないが本発明
者により検討された技術であり、その概要は次のとおり
である。The inventor has independently developed a bipolar CMOS memory. Although the following is not a publicly known technique, it is a technique considered by the present inventor, and its outline is as follows.
第５図はバイポ−ラＣＭＯＳメモリの一部、とくに０Ｍ
ＯＳとメモリセルを含む部分を示す断面図である。この
うち、バイポーラ（図示されない）や０ＭＯＳは半導体
チップにおける周辺ロジック回路を構成し、この周辺回
路に囲まれてメモリセルが形成される。Figure 5 shows a part of bipolar CMOS memory, especially 0M
FIG. 3 is a cross-sectional view showing a portion including an OS and memory cells. Among these, bipolar (not shown) and OMOS constitute a peripheral logic circuit in a semiconductor chip, and a memory cell is formed surrounded by this peripheral circuit.
同図において、１はｐ−型Ｓｉ基板、２はエピタキシャ
ル（ｎ）Ｓｉ層、３はｐウェルである。、４はアイソレ
ーシッ／酸化膜、５はアインレーシ嘗ンｐ層で各領域を
分離する。６はポリＳｉゲート、７はｐチャネルＭＯＳ
素子のソース・ドレインｐ＋層、８はｎチャネルＭＯＳ
素子のソース・ドレイ＋
ンｎ 層、９は接地電位取出しｐ 層である。１０はメ
モリセルのソース・ドレインｎ 層である。In the figure, 1 is a p-type Si substrate, 2 is an epitaxial (n) Si layer, and 3 is a p-well. , 4 is an isolation/oxide film, and 5 is an inlay p layer to separate each region. 6 is a poly-Si gate, 7 is a p-channel MOS
Source/drain p+ layer of element, 8 is n-channel MOS
The source/drain n layer 9 of the element is a p layer for taking out the ground potential. 10 is the source/drain n layer of the memory cell.
メモリセルのドレイ／ｎ 層の直下にはα線対策として
接合容量の増大をねらって高エネルギＢイオ／注入によ
るｐｉｌｌが形成される。このような構造により、基板
上に高密度・高速度のデバイスを形成することが可能で
ある。Immediately below the drain/n layer of the memory cell, a pill is formed by high-energy B ion/implantation to increase the junction capacitance as a countermeasure against alpha rays. Such a structure allows high-density, high-speed devices to be formed on the substrate.
第５図に示すバイポーラＣＭＯ＆・メモリにおいて、基
板電位が上昇し、又はｎ Ｍ ＯＳのソース（８１電位
が下ると寄生トランジスタＱ４がオンし、ソース（Ｓ）
より電子（ｅ）が注入され、ｐ−基板上を経てメモリセ
ルに電子（ｅ）が到達し、情報破壊が生じる問題があっ
た。In the bipolar CMO & memory shown in FIG.
There is a problem in that more electrons (e) are injected and reach the memory cell via the p-substrate, resulting in information destruction.
第２の問題として、第６図に示すＣＭＯＳ・メモリにお
いて、（１３基板（ｎ−）電位が下がると、寄生トラン
ジスタＱ、がオ／し、Ｒ１に電流が流れ、（２１Ｒ，に
電流が流れることによってＱｌがオンし、Ｒ１に電流が
流れ、（３１Ｒ，に電流が流れることによってＱ、がオ
ンし、Ｒ１に電流が流れる。その結果、Ｑｌ とＱ、が
オンし、ラッチアップが生じる。The second problem is that in the CMOS memory shown in Figure 6, when the (13 substrate (n-) potential decreases, the parasitic transistor Q, turns on, current flows through R1, and current flows through (21R, As a result, Ql turns on and current flows through R1, and as a result of current flowing through (31R), Q turns on and current flows through R1.As a result, Ql and Q turn on, causing latch-up.
本発明は上記した問題点を解決するためになされたもの
である。したがって本発明の一つの目的はｎ Ｍ ＯＳ
・メモリを有するデバイスにおいて情報破壊及びラッチ
アップ防止構造を提供することＫある。The present invention has been made to solve the above-mentioned problems. Therefore, one object of the present invention is to
- To provide a structure to prevent information corruption and latch-up in a device having a memory.
本発明の他の一つの目的はバイポーラＣＭＯＳメモリ又
はＣＭＯＳメモリにおいてラッチアップ防止構造を提供
することにある。Another object of the present invention is to provide a latch-up prevention structure in a bipolar CMOS memory or CMOS memory.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述及び添付図面から明らかになろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、一つの半導体基板の７主表面に少なくともｎ
チャネルＭＯＳ素子を有する周辺回路と、メモ！ｊＭＯ
Ｓ回路とを備えた半導体集積回路装置において、上記ｎ
チャネルＭＯＳ素子のソースｎ＋層直下にｐ 層が埋め
込まれたものである。That is, at least n on the seven main surfaces of one semiconductor substrate.
Peripheral circuit with channel MOS element and memo! jMO
In the semiconductor integrated circuit device equipped with the S circuit, the n
A p layer is buried directly under the source n+ layer of a channel MOS element.
ｎチャネルＭＯ３素子のソースｎ 層とその直下のｐ
層とのｐｎ接合によって基板電位上昇時、又はｎ Ｍ
ＯＳ素子のソース電位低下時に、ソースより基板へ注入
される電子の量が減少し、同じ基板のメモリ情報破壊を
防止できる。The source n layer of an n-channel MO3 device and the p layer immediately below it
When the substrate potential increases due to the pn junction with the layer, or n M
When the source potential of the OS element decreases, the amount of electrons injected from the source to the substrate decreases, making it possible to prevent memory information from being destroyed on the same substrate.
第１図は不発明の一実施例を示すものであって、一つの
半導体基体ＫＣＭＯＳ回路の一部であるｎチャネルＭＯ
ＳＦＥＴとメモリ回路が形成されたバイポーラＣＭＯＳ
メモリの一部断面図である。FIG. 1 shows an embodiment of the invention, in which an n-channel MO which is part of one semiconductor substrate KCMOS circuit is shown.
Bipolar CMOS with SFET and memory circuit formed
FIG. 3 is a partial cross-sectional view of the memory.
同図において、前掲第５図と共通する構成部分には同一
の指示記号が用いられる。In this figure, the same designation symbols are used for components common to those in FIG. 5 above.
本発明によるバイポーラＣＭＯＳメモリにおいては、ｎ
”−ＭＯＳ素子のソースｎ 層８の下にｐ＋層１２を設
けるものである。In the bipolar CMOS memory according to the invention, n
A p+ layer 12 is provided under the source n layer 8 of the ``-MOS element.
このｐ 層１２はメモリセルのドレインｎ 層１０の下
にｐ 層１１をＢ（ボロン）イオン打込みにより形成す
る際に同時Ｋ ｎ −Ｍ ＯＳ素子のソースｎ 層側に
も打込むことによって形成されるものであり、マスクの
一部を変えるのみでプロセス自体が変更されることはな
い。This p layer 12 is formed by implanting B (boron) ions into the source n layer side of the K n -MOS element at the same time as forming the p layer 11 under the drain n layer 10 of the memory cell by implanting B (boron) ions. The process itself is not changed, only a part of the mask is changed.
このような構造によれば下記の理由により効果が得られ
る。According to such a structure, effects can be obtained for the following reasons.
ｎ−ＭＯＳ素子のソースｎ 層よりｐ−基体１へ注入さ
れる電子はｐｎ接合のホール濃度によるので、ｐ 層１
２を設けることでホール濃度を高くすることにより注入
電子濃度を減らすことができる。すなわち、基板電位が
上昇したり、ｎＭ。Since the electrons injected from the source n layer of the n-MOS element into the p-substrate 1 depend on the hole concentration of the p-n junction, the p-layer 1
2, the injected electron concentration can be reduced by increasing the hole concentration. That is, the substrate potential increases or nM.
Ｓ素子ソースの電位が下がった時に、基板に注入されメ
モリセルへ到達する電子の量が減少し、したがつくメモ
リセルでの情報破壊を防止できる。When the potential of the S element source decreases, the amount of electrons injected into the substrate and reaching the memory cell decreases, thereby preventing information destruction in the memory cell.
ロジック部ｎＭＯＳ素子のドレイノ下にｐ 層を形成す
ると耐圧劣化によるブレークダウン、容量増大による信
号遅延が生じる。If a p layer is formed under the drain node of the logic part nMOS element, breakdown due to breakdown voltage deterioration and signal delay due to increased capacitance will occur.
第２図はメモリのドレイン下にｐ 層形成のために行う
Ｂイオン打込みをｎＭＯＳ素子のソース下に行う場合（
Ａ）と行わない場合とについて゛のＩＤ−ＶＤ曲線を示
すものである。Figure 2 shows the case where B ion implantation, which is performed to form a p-layer under the drain of a memory, is performed under the source of an nMOS element (
This figure shows the ID-VD curves for A) and the case where it is not carried out.
Ｂイオン打込みを行う場合（Ａ）は、Ｂイオン打込みを
行わない場合の）に比してＩＰ（ＶＦ＝０．３Ｖ）は平
均１０％程度低くなることが実験的に示された。It has been experimentally shown that when B ions are implanted (A), the IP (VF=0.3V) is about 10% lower on average than when B ions are not implanted (A).
第３図はバイポーラＣＭＯＳメモリに本発明を適用した
場合の一実施例を示し、ラッチアップ防止効果及び情報
破壊防止効果を説明するための断面図である。FIG. 3 shows an embodiment in which the present invention is applied to a bipolar CMOS memory, and is a sectional view for explaining the latch-up prevention effect and the information destruction prevention effect.
同図において前掲第５図、第１図と共通する構成部分に
は同一の指示記号が用いである。In this figure, the same reference symbols are used for components common to those in FIG. 5 and FIG. 1 described above.
１３はｎ 埋込層、１４はバイポーラｎｐｎ）ランジス
タのベースｐ 層、１５は同エミッタｎ＋層、１６は同
コレクタ取出しｎ 層である。13 is an n buried layer, 14 is a base p layer of a bipolar npn transistor, 15 is an emitter n+ layer, and 16 is a collector extraction n layer.
このバイポーラＣＭＯＳメモリにおいて、バイポーラト
ランジスタの飽和をとりだしたラッチアップ及び情報破
壊は、下記の形態で行われる。In this bipolar CMOS memory, latch-up and information destruction caused by saturation of the bipolar transistor are performed in the following manner.
（ａ） ラッチアップの場合
（１）ｎｐｎ）ランジスタが飽和してＱ、がオンすると
、Ｒｔ Ｒｓを通してＧＮＤで基板電流が流れる。(a) In the case of latch-up (1) npn) When the transistor is saturated and Q is turned on, a substrate current flows through Rt and Rs to GND.
（２） Ｒｓに電流が流れることによってＱ、がオン
する。Ｒ２に電流が流れる。(2) When current flows through Rs, Q turns on. Current flows through R2.
（３） Ｒ４に電流が流れることによってＱ、がオン
する。Ｒ８に電流が流れる。Ｑ、とＱ、がオンしてラッ
チアップが生じようとする。(3) When current flows through R4, Q is turned on. Current flows through R8. Q and Q turn on and latch-up is about to occur.
しかし、本発明ではｎ Ｍ ＯＳ素子のソースの下側に
ｐ ＃ｉ１２を設けることＫよりてＱ３のＶＢＥを上
げる。したがってラッチアップしＫ＜くなる。However, in the present invention, the VBE of Q3 is increased by providing p #i12 below the source of the nMOS device. Therefore, latch-up occurs and K<.
（ｂ） 情報破壊の場合
基板電位が上又はｎＭＯＳのソース電位が下がると、Ｑ
、がオンし情報破壊を生じるような場合、本発明ではｐ
層１２を設けることで破壊を防止できる。このような
構造によれば基板に注入される電子によって不良となる
高電源電圧のマージンを向上できる。(b) In the case of information destruction, if the substrate potential rises or the nMOS source potential falls, Q
, which turns on and causes information destruction, in the present invention, p
By providing the layer 12, destruction can be prevented. With such a structure, it is possible to improve the margin of a high power supply voltage that becomes defective due to electrons injected into the substrate.
第４図はＣＭＯＳメモリに本発明を適用した場合の一実
施例を示すラッチアップ防止効果を説明するための断面
図である。FIG. 4 is a cross-sectional view for explaining the latch-up prevention effect showing an embodiment of the present invention applied to a CMOS memory.
このようなＣＭＯＳメモリにおけるラッチアップ現象に
ついては、第６図で既に説明した通りである。The latch-up phenomenon in such a CMOS memory has already been explained with reference to FIG.
本発明ではｎＭＯＳ素子のソースの下側にｐ＋層１２を
入れることによって寄生トランジスタＱ１のｖＢＥを上
げよってラッチアップ防止かできる。In the present invention, latch-up can be prevented by increasing the vBE of the parasitic transistor Q1 by inserting the p+ layer 12 under the source of the nMOS element.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能である。Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof.
本発明はバイポーラＣＭＯＳメモリあるいはＣＭＯＳメ
モリに適用して有効である。The present invention is effective when applied to bipolar CMOS memory or CMOS memory.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば下記のとおりである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、ｎ Ｍ ＯＳメモリにおいて基板電位上昇時
の情報破壊を防ぎ、ラッチアップ防止ができる。That is, in the nMOS memory, information destruction can be prevented when the substrate potential increases, and latch-up can be prevented.
第１図は本発明の一実施例を示すｎ Ｍ ＯＳメモリの
断面図である。
第２図は不純注入効果を示す電流電圧特性曲線図である
。
第３図は本発明の他の一実施例を示すバイポーラＣＭＯ
Ｓメモリの断面図である。
第４図は本発明のさらに他の実施例を示すＣＭＯＳメ七
りの断面図である。
第５図、第６図は従来のＣＭＯＳメモリにおけるラッチ
アップ効果を説明するための断面図である。
１・・・ｐ”−８ｉ基板、２・・・エピタキシャルｎ層
、３・・・ｐウェル、４・・・アイソレージ１ノ酸化膜
、６・・・Ｓｉゲー）、７・・・ソース・ドレインｐ層
、８・・・ソース・ドレインｎ 層、９・・・基板電位
取出し＋
ｐ 層、ｌＯ・・・メモリのドレインｎＪｉ、ｉｔ・・
・メそりのドレイン下ｐ 層、１２・・・ｎ Ｍ ＯＳ
のソース下ｐ 層。
代理人 弁理士 小 川 勝 男
第１図
第 ２ 図FIG. 1 is a sectional view of an nMOS memory showing an embodiment of the present invention. FIG. 2 is a current-voltage characteristic curve diagram showing the impurity injection effect. FIG. 3 is a bipolar CMO showing another embodiment of the present invention.
It is a sectional view of S memory. FIG. 4 is a sectional view of a CMOS transistor showing still another embodiment of the present invention. FIGS. 5 and 6 are cross-sectional views for explaining the latch-up effect in conventional CMOS memories. DESCRIPTION OF SYMBOLS 1...p"-8i substrate, 2...Epitaxial n layer, 3...P well, 4...Isolation oxide film, 6...Si game), 7...Source/drain p layer, 8...source/drain n layer, 9...substrate potential extraction +p layer, lO...memory drain nJi, it...
・P layer under mesori drain, 12...n M OS
source of lower p-layer. Agent: Patent Attorney Katsoo Ogawa Figure 1 Figure 2
Claims (1)
ルＭＯＳ素子を有する回路と、この回路に近接してメモ
リセルとを備えた半導体集積回路であって上記ｎチャネ
ルＭＯＳ素子のソースｎ＾＋領域下にｐ＾＋層が埋め込
まれていることを特徴とする半導体集積回路装置。 ２、上記メモリセルのドレインとなるｎ＾＋領域直下に
ｐ＾＋層が埋め込まれ、上記ｎチャネルＭＯＳ素子のソ
ース領域下のｐ＾＋層は上記ドレイン下のｐ＾＋層形成
のための不純物と同時に導入されたものである特許請求
の範囲第１項に記載の半導体集積回路装置。[Scope of Claims] 1. A semiconductor integrated circuit comprising a circuit having at least an n-channel MOS element on one main surface of one semiconductor substrate, and a memory cell adjacent to this circuit, wherein the n-channel MOS element A semiconductor integrated circuit device characterized in that a p^+ layer is embedded under a source n^+ region. 2. A p^+ layer is buried directly under the n^+ region which becomes the drain of the memory cell, and the p^+ layer under the source region of the n-channel MOS element is used for forming the p^+ layer under the drain. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is introduced simultaneously with an impurity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61281730A JPS63136663A (en) | 1986-11-28 | 1986-11-28 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61281730A JPS63136663A (en) | 1986-11-28 | 1986-11-28 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63136663A true JPS63136663A (en) | 1988-06-08 |
Family
ID=17643181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61281730A Pending JPS63136663A (en) | 1986-11-28 | 1986-11-28 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63136663A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107039458A (en) * | 2015-11-04 | 2017-08-11 | 德州仪器公司 | The construction of hall effect sensor in isolated area |
-
1986
- 1986-11-28 JP JP61281730A patent/JPS63136663A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107039458A (en) * | 2015-11-04 | 2017-08-11 | 德州仪器公司 | The construction of hall effect sensor in isolated area |
| CN107039458B (en) * | 2015-11-04 | 2022-12-20 | 德州仪器公司 | Construction of Hall Effect sensors in isolation regions |
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