JPS63136526A - Dry etching method - Google Patents
Dry etching methodInfo
- Publication number
- JPS63136526A JPS63136526A JP28076086A JP28076086A JPS63136526A JP S63136526 A JPS63136526 A JP S63136526A JP 28076086 A JP28076086 A JP 28076086A JP 28076086 A JP28076086 A JP 28076086A JP S63136526 A JPS63136526 A JP S63136526A
- Authority
- JP
- Japan
- Prior art keywords
- gas
- hole
- etching
- chamber
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000001312 dry etching Methods 0.000 title claims abstract description 15
- 239000007789 gas Substances 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 150000001875 compounds Chemical class 0.000 claims abstract description 6
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims abstract description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 29
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 17
- 229910052751 metal Inorganic materials 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910015844 BCl3 Inorganic materials 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 238000001020 plasma etching Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- YPSXFMHXRZAGTG-UHFFFAOYSA-N 4-methoxy-2-[2-(5-methoxy-2-nitrosophenyl)ethyl]-1-nitrosobenzene Chemical compound COC1=CC=C(N=O)C(CCC=2C(=CC=C(OC)C=2)N=O)=C1 YPSXFMHXRZAGTG-UHFFFAOYSA-N 0.000 description 1
- 102100021569 Apoptosis regulator Bcl-2 Human genes 0.000 description 1
- 241001012508 Carpiodes cyprinus Species 0.000 description 1
- 101000971171 Homo sapiens Apoptosis regulator Bcl-2 Proteins 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 1
- 235000019404 dichlorodifluoromethane Nutrition 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 210000001061 forehead Anatomy 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は化合物半導体基体のドライエツチング方法に係
り、特にエツチングガスの成分に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for dry etching a compound semiconductor substrate, and particularly to the components of an etching gas.
(従来の技術)
半導体基体をガス中でエツチングするいわゆるドラ・イ
エノチング力法は、従来からのクエットエッチング力法
に比べて微細加工性、再現性に優れ、又エツチングムラ
が少ない事や後処理において多量の水を使わずにすむた
めに汚染を受けにくい等有利な点が多い。さらにドライ
エツチング法はマスクを選択的に設けてエツチングを行
なった場合に、マスクに接した半導体基体への横力向へ
のエツチング社、すな0ちサイドエツチングを小さくす
ることができ、かつエツチング断面形状をほぼ垂直に近
い形大てすることを可能にする方法として注目されてい
る。 このため最近の半導体素子製作工程における1つ
のグロセスとしてざがんに使われ、例えばGaA s
MM I Cの製造における半導体基体の加工や電極の
形成にはかかせない技術となってきている。(Prior technology) The so-called dry etching force method, which etches a semiconductor substrate in a gas, has superior microfabrication performance and reproducibility compared to the conventional Couette etching force method, and also has less uneven etching and is easier to use in post-processing. It has many advantages, such as being less susceptible to contamination because it does not require the use of large amounts of water. Furthermore, in the dry etching method, when etching is performed with a mask selectively provided, it is possible to reduce etching in the direction of lateral force on the semiconductor substrate in contact with the mask, that is, side etching. This method is attracting attention as a method that allows the cross-sectional shape to be enlarged to a nearly vertical shape. For this reason, it is widely used as a gross process in the recent semiconductor device manufacturing process, for example, GaAs
It has become an indispensable technology for processing semiconductor substrates and forming electrodes in the production of MMICs.
ドライエツチングを用いる一例として半導体基体にピア
ホールを形成する過程を述べる。ピアホールは、PET
のソースインダクタンスヲ低減させるために半導体基体
裏面より表面に貫通する穴を開口させ、この穴にソース
金属を埋めて表面側のソース電極と基体裏面を電気釣に
接続させる技術であり、このためには垂直エツチング可
能ナトライエツチングである反応性1′オンエンテング
(RIE)が有効である。RIEによるピアホール形成
は例えば” J 、 Vac 、Sci 、Techn
ol 、 B3 fl)Jan/Feb 1985
、 P 355〜’4に報告されている。As an example of using dry etching, the process of forming a peer hole in a semiconductor substrate will be described. Pier hole is PET
In order to reduce the source inductance of a semiconductor substrate, a hole is opened that penetrates from the back surface to the surface, and this hole is filled with source metal to connect the source electrode on the front side and the back surface of the substrate by electrostatic fishing. Reactive 1' on-entetching (RIE), which is a vertically etchable natri etching method, is effective. Peerhole formation by RIE is described in, for example, "J, Vac, Sci, Techn.
ol, B3 fl) Jan/Feb 1985
, P 355-'4.
以下本発明の従来例として、R,IE法によシGaAs
基体にピアホールを形成するだめの貫通孔を形成する場
合について述べる。従来、()aAs基体にピアホール
を形成するには、70・ン12(CC12F2)ガス、
CCl2F2ガスと02ガスとの混合ガス、BCg3と
C1,との混合ガスが用いられてきた。ここではエツチ
ング残渣が少ないB C13とC20との混合カスを用
いて貫通孔を形成する場合について第3図tal〜第3
図tc)の工程断面図を用いて述べる。Below, as a conventional example of the present invention, GaAs was prepared by the R, IE method.
A case will be described in which a through hole for forming a peer hole is formed in the base body. Conventionally, in order to form a pier hole in a ()aAs substrate, 70·n12 (CC12F2) gas,
A mixed gas of CCl2F2 gas and 02 gas, and a mixed gas of BCg3 and C1 have been used. Here, we will discuss the case of forming through holes using a mixture of B C13 and C20 with less etching residue.
This will be explained using the process cross-sectional view in Figure tc).
第3図ta)に示すように面方位(100)、厚さ10
0μmの(jaAs牛導体基体]の表面にエツチングガ
スクとなる5i01膜2を堆積し、このSiO□膜2を
選択的に除去することにより30μm真の穴を開口させ
てGaAs基体1の表面を露出する。As shown in Figure 3 (ta), the surface orientation is (100) and the thickness is 10.
A 5i01 film 2 serving as an etching gas is deposited on the surface of a 0 μm (jaAs conductive substrate), and this SiO□ film 2 is selectively removed to open a 30 μm true hole and expose the surface of the GaAs substrate 1. do.
又、GaAs基体1の表面に貫通の際エツチングガスの
回り込みを防ぐだめの保護膜3を設ける。次にこのGa
As基体1をエツチングチェンバー甲に入れて真空排気
を行った後、B C1、ガスとC1,ガスを各h20C
C/min、2CC/minの割合で尋人する。次にR
,F’を力を例えば480W加えてガスを活性化させて
、選択的に露出したGaAs基体】の裏面を第3図fb
)、 tc)に示すような貫通孔4を形成する。Further, a protective film 3 is provided on the surface of the GaAs substrate 1 to prevent the etching gas from going around during the etching process. Next, this Ga
After putting the As substrate 1 into the etching chamber A and performing vacuum evacuation, the B C1 gas and the C1 gas were heated to h20C.
C/min, 2CC/min. Then R
, F' is applied with a force of, for example, 480 W to activate the gas, and the back surface of the selectively exposed GaAs substrate is exposed as shown in Fig. 3fb.
), tc) are formed.
ここで第3図fb)はく0】1〉方向から見た貫通孔4
01析而図であり、第3図(C)は<011>方向から
見た貫通孔4の断面図である。第3図(blに示すよう
にB (1,ガスとC12ガスとの混合ガスによりエツ
チングして貫通孔4を形成した揚台、貫通孔の形状は逆
テーパ、すなわち貫通孔の側壁の5iO1膜2に対する
角度θが鋭角になる。エツチングWr面形伏がこのよう
に逆テーパになると貫通孔形成後、真空蒸着法によりソ
ース金部同志を相互に電気的に接続する工程に2いて、
蒸着された金属が貫通孔内全体に広がらないため、電気
的接続が不完全なものとなる。Here, the through hole 4 seen from the direction of Figure 3fb)
01 analysis diagram, and FIG. 3(C) is a sectional view of the through hole 4 seen from the <011> direction. As shown in Figure 3 (bl), B (1) The platform is etched with a mixed gas of gas and C12 gas to form a through hole 4. The shape of the through hole is a reverse taper, that is, the 5iO1 film on the side wall of the through hole. The angle θ with respect to 2 becomes an acute angle.If the etched Wr surface shape becomes inversely tapered in this way, after forming the through hole, in the step 2 of electrically connecting the source metal parts to each other by vacuum evaporation,
The electrical connection is incomplete because the deposited metal does not spread throughout the through hole.
又、第3図tc)に示すように従来法ではエツチングが
横力向に大きく広がり、そのサイドエツチングtC第3
図fc)において!で示す)は例えばウェットエツチン
グの場合の100μmに比べて40μm、と改善されて
はいるもののまだ不十分である。In addition, as shown in Fig. 3 (tc), in the conventional method, the etching spreads greatly in the direction of the lateral force, and the side etching tC3
In figure fc)! ) is 40 μm compared to 100 μm in the case of wet etching, which is an improvement, but is still insufficient.
したがって、エツチングして貫通孔を形成する際近接し
ている他の貫通孔に重ならないようにするためにはマス
ク開口部間の間隔を広げる必要がある。このことはピア
ホールを形成するためには、FETのソース電極同志の
間隔を広げてFETパターンを設計する必要があり、余
分なソース抵抗及ヒソースインダクタンスが増すという
問題がある。さらにパターン配置上集積度が者しく低下
し高密度設計のための自由度がなくなる。Therefore, when forming a through hole by etching, it is necessary to widen the interval between the mask openings in order to avoid overlapping other adjacent through holes. This poses a problem in that in order to form a peer hole, it is necessary to design a FET pattern by widening the distance between the source electrodes of the FET, which increases extra source resistance and source inductance. Furthermore, the degree of integration decreases significantly in terms of pattern arrangement, and the degree of freedom for high-density design is lost.
(発明が解決しようとする問題点)
以上述べたように従来のドライエツチング法において用
いられているB C1,ガスとCI、ガスとの混合ガス
により、ピアホール形成のための貫通孔を形成すると貫
通孔が逆テーパ吠になり、又サイドエツチングが大きい
ために電気的接続が不完全となるばかシか集積度が向上
しないという問題点があった。(Problems to be Solved by the Invention) As mentioned above, when a through hole for forming a pier hole is formed using a mixed gas of B C1 gas and CI gas used in the conventional dry etching method, There are problems in that the holes have a reverse taper shape and the side etching is large, resulting in incomplete electrical connections and failure to improve the degree of integration.
(問題点を解決するための手段)
上記目的を達成するために本発明では、エツチングガス
としてBCI、ガスとC6,ガスとの混合ガスを用いる
化合物子導体基体のドライエツチング方法において、混
合ガス中に窒素ガスを范加することを特徴とするドライ
エツチング方法を提供することを目的とする。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a dry etching method for a compound conductor substrate using BCI as an etching gas and a mixed gas of gas and C6 gas. An object of the present invention is to provide a dry etching method characterized by adding nitrogen gas to the dry etching method.
(作用)
本発明者はG a A s基体にパイγホールを形成す
る工程において上記の粂件を適用して果暎を行った。第
1図がその結果であり、(jaA s基体をく011〉
方向から見た場合も、<O] 1>方向から見た場合も
GaAs基体に形成された貫通孔は11貝テーパ吠にな
る。これはN2ガスがBCl3ガスと反応してBNが生
成され、エツチングが抑制されることによりGaAs基
体の絽出面側が反対面よりエツチング量が多くなり貫通
孔iす順テーパ伏に形成されると推定される。(Function) The present inventor applied the above-mentioned method to the process of forming pi-γ holes in a GaAs substrate. Figure 1 shows the results.
The through hole formed in the GaAs substrate has a tapered shape when viewed from the <O]1> direction as well. It is assumed that this is because N2 gas reacts with BCl3 gas to generate BN, which suppresses etching, resulting in a larger amount of etching on the exposed surface of the GaAs substrate than on the opposite surface, forming a tapered shape in the order of the through hole i. be done.
(実施例)
以下不発明の一つの実施列とし℃、従来例と同じ((J
aAs半纏体基体に貫通孔を形成する場合につき図面を
参照して説明する。本発明では第3図ialに示したG
a A s半導体基体1を使用する。すなわち、面方位
(100)、厚G ] 00 ttmのG a A S
午4体基体】の裏面にエツチングマスクとなる5i0
2膜2を堆積し、この5i02膜2を選択的に除去する
ことにより30μmlの穴を開口させてGaAs基体】
の裏面を露出する。さらにGaAs 基体1の表面に貫
通の際、エツチングガスの回り込みを防ぐためのエツチ
ングストッパとなる金属、り1」えばA u / P
t / T iからなる保設置臭3を設ける。(Example) The following is an example of an uninvented implementation sequence.℃, the same as the conventional example ((J
The case of forming a through hole in an aAs semi-integrated substrate will be explained with reference to the drawings. In the present invention, G shown in FIG.
a As semiconductor substrate 1 is used. That is, G a A S with plane orientation (100) and thickness G ] 00 ttm
5i0 which becomes an etching mask on the back side of [4 body base]
2 film 2 is deposited, and this 5i02 film 2 is selectively removed to open a 30 μml hole to form a GaAs substrate]
expose the back side of. Further, when penetrating the surface of the GaAs substrate 1, a metal, for example A u / P, is used as an etching stopper to prevent the etching gas from going around.
A storage odor 3 consisting of T/T i is provided.
そこでこの試料をRIE装置のチャンバー内に入れ、チ
ャンバー内の圧力を5X10 Pa以下に排気して不
純物ガスを取り除く。続いてN2ガスを圧力が7X10
Paになるまでチャンバー内に弄スした後、B(J
3ガスとC/2ガスを各々20CC/min、2 CC
/minの割合でチャンバー内に尋人する。この時のチ
ャンバー内の圧力は1.7Paになるように排気量を調
整する。次にBP’電力を480W711]えてガスを
活性化させて5iOzマスク開口部を60分間エツチン
グしてGaAs基体1に貫通孔4′を形成する。Therefore, this sample is placed in a chamber of an RIE apparatus, and the pressure in the chamber is evacuated to 5×10 Pa or less to remove impurity gas. Next, add N2 gas to a pressure of 7X10.
After stirring in the chamber until Pa, B (J
3 gas and C/2 gas at 20 CC/min each, 2 CC
/min into the chamber. At this time, the exhaust volume is adjusted so that the pressure inside the chamber is 1.7 Pa. Next, the BP' electric power was changed to 480W, 711W to activate the gas, and the 5iOz mask opening was etched for 60 minutes to form the through hole 4' in the GaAs substrate 1.
このようにして得られた貫通孔の断面の形状は、第1図
に示すように(011>方向から見た場合にはj1hテ
ーパ、すなわち貫通孔4′の側壁の5i02膜に対する
角度θ′が鈍角になる。又、く01]〉方向から見た貫
通孔4′の形状も第1図に示したものと同様に順テーパ
になる。これはN2ガスがB(J、ガスと反応してBN
が生成され、エツチングが抑制されることによりQ a
A s 4G、体1の露出面側が反対面よりエツチン
グ蓋が多くなり貫通孔4′は順テーパ伏に形成されると
推定される。The shape of the cross section of the through hole obtained in this way is as shown in FIG. In addition, the shape of the through hole 4' when viewed from the 01]> direction also becomes a forward taper similar to that shown in Fig. 1.This is because the N2 gas reacts with the B(J, gas). B.N.
is generated and etching is suppressed, resulting in Q a
A s 4G, it is estimated that there are more etched lids on the exposed side of the body 1 than on the opposite side, and the through hole 4' is formed in a downwardly tapered shape.
したがって、貫通孔4′が順テーパ伏に形成されるので
、ソース金輿同志を相互に電気的に接続する後工程にお
いて、GaAs基体101に額より真空蒸着を行った場
合に蒸着された金属が貫通孔4′内全体に広がり電気的
接続が完全なピアホールの形成が可能洸なる。Therefore, since the through-hole 4' is formed in a downwardly tapered manner, the metal deposited when vacuum evaporation is performed from the forehead on the GaAs substrate 101 in the post-process of electrically connecting the source metals to each other is It becomes possible to form a pier hole that extends throughout the through hole 4' and has a complete electrical connection.
第2図ta+ 、 tb)は上記方法によりGaAs基
体1に貫通孔4′を形成した場合の平面図であり、第2
図(a):ま保護膜3を除去して貫通孔4′を露出させ
て表面より見た図であり、又第2図+b)は裏面より5
iO1膜を通して児た図である。第2図(a)に示すよ
うに貫通孔4′の表面の形状は30 nmダでエツチン
グマスク径と同じ形状、同じ大きさである。又、裏面の
形状はエツチングマスク径(第2図+b)の点綴部分)
の30μmlに対して、貫通孔4′の矢面は60μml
である。したがってサイドエツチング電は15μmであ
り従来に比べて大幅に減少する。FIG. 2 (ta+, tb) is a plan view when the through hole 4' is formed in the GaAs substrate 1 by the above method.
Figure (a): This is a view from the front side with the protective film 3 removed to expose the through hole 4', and Figure 2+b) is a view from the back side.
FIG. 3 is a diagram showing a view through the iO1 membrane. As shown in FIG. 2(a), the surface shape of the through hole 4' is 30 nm in diameter, which is the same shape and size as the etching mask diameter. Also, the shape of the back side is the dotted part of the etching mask diameter (Figure 2 + b))
30μml, the brunt of the through hole 4' is 60μml
It is. Therefore, the side etching current is 15 μm, which is significantly reduced compared to the conventional method.
又、本発明者i丁同様の実験を数回繰シ返したが、貫通
孔4′の形状は常に第1図のよって断面がI$1′r−
バで、平面が第2図(a)、 tb)のようにa、b、
極めて再現性よく本発明の効果が得られることが確認さ
れた。In addition, although the inventor repeated the same experiment several times, the shape of the through hole 4' always had a cross section of I$1'r- as shown in FIG.
In the bar, the planes are a, b, as shown in Figure 2 (a), tb).
It was confirmed that the effects of the present invention can be obtained with extremely good reproducibility.
なお、B(1,ガスとC12ガスとの混合ガスにN2ガ
スを添加する際、N2ガスのiはドライエツチング装置
へエツチング条件等によシ異なるために最適量ハこれら
の諸条件に応じて決定する必要がある。又N2ガスを適
重以上に添加するとサイドエツチングが大きくなるとい
う結果が得られている。Note that when adding N2 gas to a mixed gas of B(1) gas and C12 gas, the i of the N2 gas varies depending on the etching conditions of the dry etching device, so the optimum amount should be determined according to these conditions. Furthermore, it has been found that side etching increases when N2 gas is added in an amount greater than the appropriate weight.
又、上述した実施例ではエツチング装置として凡IE装
置を用いる場合を示したが、本発明はエツチング装置に
何ら抱束されるものではなくBCl、ガスとC12ガス
を用いて行なう別の装置、例えば反応性イオンビームエ
ツチング(RIBE)装置等を用いても同等の効果が得
られる。さらに禎処理半纏体基体についてもGaAsに
限定されるものではなく、広く化合物子導体基体全般に
不発明を適用することができる。Further, in the above-described embodiment, a case was shown in which an ordinary IE apparatus was used as the etching apparatus, but the present invention is not limited to the etching apparatus in any way, but may be performed using another apparatus using BCl gas and C12 gas, for example. A similar effect can be obtained by using a reactive ion beam etching (RIBE) device or the like. Further, the semi-solid substrate subjected to heat treatment is not limited to GaAs, and the invention can be applied to a wide range of compound conductor substrates in general.
以上述べたように本発明によれば、BCl2ガスとC1
,ガスとの混合ガスにN、ガスを6加して化合物半導体
基体のドライエツチングを行うことにより、エツチング
された貫通孔の形状が順テ−パに形成されるので、化合
物半導体基体にピアホールを形成するに好適なドライエ
ツチング方法を提供できる。As described above, according to the present invention, BCl2 gas and C1
By dry etching the compound semiconductor substrate by adding N and gas to the mixed gas, the etched through hole is formed in a forward tapered shape. It is possible to provide a dry etching method suitable for forming.
第1図は本発明によるドライエツチング方法により形成
された貫通孔の(011)方向から見た断面図、第2図
talは本発明によシ形成された貫通孔の面方位(10
0)の平面図、第2図(b)は本発明により形成された
貫通孔の面方位(100)び2
の平面図、第3図ta+乃至(5)は従来のドライエツ
チング方法により形成される貰曲孔の工程断面図である
。
1−=GaAs#−j4体基体、2 ・−S i02膜
、3・・保4膜、4.4′・・・貫通孔。
代理人 弁理士 則 近 患 佑
同 竹 花 喜久男
茅 1 口
ノ59L&
舅2 ロFIG. 1 is a sectional view of a through hole formed by the dry etching method according to the present invention, viewed from the (011) direction, and FIG.
0), FIG. 2(b) is a plan view of the plane orientation (100) and 2 of the through hole formed according to the present invention, and FIG. It is a process sectional view of the bent hole. 1-=GaAs#-j4 body substrate, 2.-Si02 film, 3..4 film, 4.4'... through hole. Agent Patent Attorney Chika Nori Yudo Takehana Kikuo Kaya 1 Kuchino 59L & Father-in-law 2ro
Claims (1)
混合ガスを用いる化合物半導体基体のドライエッチング
方法において、前記混合ガス中に窒素ガスを添加するこ
とを特徴とするドライエッチング方法。A dry etching method for a compound semiconductor substrate using a mixed gas of boron trichloride gas and chlorine gas as an etching gas, characterized in that nitrogen gas is added to the mixed gas.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28076086A JPS63136526A (en) | 1986-11-27 | 1986-11-27 | Dry etching method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28076086A JPS63136526A (en) | 1986-11-27 | 1986-11-27 | Dry etching method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63136526A true JPS63136526A (en) | 1988-06-08 |
Family
ID=17629570
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28076086A Pending JPS63136526A (en) | 1986-11-27 | 1986-11-27 | Dry etching method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63136526A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5527425A (en) * | 1995-07-21 | 1996-06-18 | At&T Corp. | Method of making in-containing III/V semiconductor devices |
-
1986
- 1986-11-27 JP JP28076086A patent/JPS63136526A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5527425A (en) * | 1995-07-21 | 1996-06-18 | At&T Corp. | Method of making in-containing III/V semiconductor devices |
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