JPS6313538A - Transmission and reception circuit - Google Patents

Abstract

PURPOSE:To effectively attain consecutive data transmission by controlling the input or output of a buffer depending on the occupied or idle state of the buffer if the timing frequency of a sending and receiving side differs. CONSTITUTION:The data 2 outputted from a transmission circuit 1 are stored in a buffer storage circuit 7 in the sending timing 3, the stored data 2 are read in the reception timing outputted from a reception circuit 4 and received as data 5. If the reception timing frequency is larger than the transmission timing frequency, the buffer storage circuit 7 is filled up at any time. The state is detected by a control circuit 8 to stop the input of the data 2 and after a prescribed reception timing elapses, the input of the data 2 is restarted. If the reception timing frequency is smaller than the transmission timing frequency, the buffer is idle at any time. The state is detected by the control circuit 8 to stop the read of the data 5, a mark bit '1' is outputted and the sending of the data 5 is restarted after a prescribed sending timing number elapses.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transmitting/receiving circuit when the timing frequencies of the transmitting side and the receiving side are different in transmitting and receiving data.

[Conventional technology]

Conventionally, in this type of transmitter/receiver circuit, the transmitter side.

If the receiving side timing frequencies are different, during sending and receiving,
It can be applied to relatively short intermittent data transmission and reception where the buffer does not become full or empty.

[Problems to be Solved by the Invention] In the conventional transmitting/receiving circuit described above, a deviation in timing occurs in the data from a certain point in time, that is, when the buffer is full or the buffer is empty, and data cannot be transmitted and received correctly thereafter. There is a drawback.

SUMMARY OF THE INVENTION An object of the present invention is to provide a transmitting/receiving circuit that eliminates such drawbacks and can correctly transmit and receive only a predetermined buffer amount of data by interposing a buffer between the transmitting and receiving circuits.

[Means for solving problems]

The configuration of the present invention provides a transmitting/receiving circuit including a transmitting circuit that transmits data at a predetermined transmitting timing and a receiving circuit that inputs data at a receiving timing of a frequency different from the transmitting timing. a buffer storage circuit that receives and stores the data at the transmission timing and reads and outputs the data at the reception timing from the reception circuit; and a buffer storage circuit that detects whether the buffer is full or empty as the buffer storage state of the buffer storage circuit and determines whether the buffer is full or not. The present invention is characterized by comprising a control circuit that stops inputting data from the transmitting side to the buffer for a certain period of time, and stops outputting data from the buffer to the receiving side for a certain period of time when it is empty.

[Example] Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This embodiment is composed of a transmitting circuit 1, a receiving circuit 4, a buffer storage circuit 7, and a control circuit 8. First, transmitting circuit 1
The data 2 outputted from the buffer storage circuit 7 is stored in the buffer storage circuit 7 at the transmission timing 3. This accumulated data 2 is read out at reception timing 6 output from the reception circuit 4,
Received as data 5.

(+) When the reception timing frequency is greater than the transmission timing frequency, the transmission timing frequency is small, and the buffer storage circuit 7
As more data is input to the buffer storage circuit 7, the buffer storage circuit 7 will eventually become full. The control circuit 8 detects this state and stops inputting the data 2.

The receiving circuit 4 continues to read the received data 5 at the receiving timing 6, and resumes inputting the data 2 after a certain number of receiving timings have elapsed. During this period (a certain number of reception timings), the input data is discarded, but the error is localized based on parse 1.

(2) When the reception timing frequency is smaller than the transmission timing frequency, the reception timing frequency is small and the buffer storage circuit 7
As more data is read from the buffer, the buffer will eventually become empty. The control circuit 8 detects this state, stops reading the data 5, and outputs a mark pip I "1". The transmitting circuit 1 continues to input the transmitting data 2 at the transmitting timing 3,
After a certain number of transmission timings have elapsed, transmission of data 5 is resumed. During this period (a certain number of transmission timings), the output data is marked with I-r 1. This means that J has been inserted, and the error has been localized in terms of verse I.

〔Effect of the invention〕

As described below, the present invention localizes bit errors in bursts by controlling the input or output of the buffer from the full or empty state when the timing frequencies of the transmitting and receiving sides are different. Therefore, continuous data transmission, such as periodically repeating the same information, can be effectively performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Transmission circuit, 2... Transmission data, 3... Transmission timing, 4... Receiving circuit, 5... Reception data,
6... Reception timing, 7... Buffer storage circuit,
8...Control circuit. −6≧

Claims (1)

[Claims] A transmitting/receiving circuit including a transmitting circuit that transmits data at a predetermined transmitting timing, and a receiving circuit that inputs data at a receiving timing of a frequency different from the transmitting timing,
A buffer storage circuit that receives and stores data from the transmission circuit at the transmission timing, reads and transmits the data at the reception timing from the reception circuit, and detects whether the buffer storage circuit is full or empty as a buffer storage state. and a control circuit that stops inputting data from the transmitting side to the buffer for a certain period of time when the buffer is full, and stops outputting data from the buffer to the receiving side for a certain period of time when it is empty. .