JPS63135009A - Distributer - Google Patents

Distributer

Info

Publication number
JPS63135009A
JPS63135009A JP28141286A JP28141286A JPS63135009A JP S63135009 A JPS63135009 A JP S63135009A JP 28141286 A JP28141286 A JP 28141286A JP 28141286 A JP28141286 A JP 28141286A JP S63135009 A JPS63135009 A JP S63135009A
Authority
JP
Japan
Prior art keywords
distribution circuit
capacitors
choke coil
circuit
distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28141286A
Other languages
Japanese (ja)
Inventor
Yoshihiro Tanigawa
嘉浩 谷川
Keiichi Mizuguchi
水口 慶一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP28141286A priority Critical patent/JPS63135009A/en
Publication of JPS63135009A publication Critical patent/JPS63135009A/en
Pending legal-status Critical Current

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  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Abstract

PURPOSE:To improve the VSWR in the reduction of a transmission frequency region by setting a resonance frequency of a parallel resonance circuit comprising both capacitors and a choke coil in the vicinity of the lower limit of the transmission frequency band of the titled distribution circuit. CONSTITUTION:The distribution circuit 1 distributing an input signal to a couple of outputs, DC blocking capacitors C1, C2 inserted respectively to an input terminal and an output terminal of the distribution circuit 1 and a choke coil RFC for high frequency blocking connected between terminals at the opposite side of the distribution circuit 1 in the capacitors C1, C2 constitute the titled distributer. In this case, the resonance circuit comprising the choke coil RFC and the capacitors C1, C2 is used as the parallel resonance circuit and the resonance frequency is set in the vicinity of the lower limit of the transmission frequency band of the distribution circuit 1. Since the matching at the input terminal is taken well even near the lower limit of the transmission frequency band, the VSWR is improved.

Description

【発明の詳細な説明】 [技術分野J 本発明は、高周波入力信号を複数の出力に分配する分配
器に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field J] The present invention relates to a distributor that distributes a high frequency input signal to a plurality of outputs.

[背景技術] 従来よりこの種の分配器としては、出力側からブースタ
への給電が行なえるように電流通過型の構成としたもの
が提供されており、第1図に示すように、入力信号を複
数の出力に分配する分配回路1と、分配回路1の入力端
および1つの出力端にそれぞれ一端が接続された一対の
直流阻止用のコンデンサC,,C2と、両コンデンサC
,,C2の他端間に接続された高周波阻止用のチョーク
コイルRFCとから植成されている。すなわち、ブース
タに給電するための直流は、出力端子01と入力端子■
との間でチョークコイルRFCを介して流れるのであり
、また入力端子Iから出力端子01への高周波の入力信
号は分配回路1を通して分配されるようになっている。
[Background Art] Conventionally, this type of distributor has been provided with a current passing type configuration so that power can be supplied to the booster from the output side, and as shown in Fig. 1, the input signal is A distribution circuit 1 that distributes the output to a plurality of outputs, a pair of DC blocking capacitors C, C2, one end of which is connected to the input terminal and one output terminal of the distribution circuit 1, and both capacitors C.
, , and a high frequency blocking choke coil RFC connected between the other ends of C2. In other words, the direct current for feeding the booster is output terminal 01 and input terminal ■
The high frequency input signal from the input terminal I to the output terminal 01 is distributed through the distribution circuit 1.

ところで、分配回路1を通して伝送される高周波信号は
、従来ではFM放送ないしUHF放送の帯域、すなわち
76〜770MHzを含むように設定すればよいもので
あったが、最近ではHF帯を含む5〜76MHzの信号
も伝送する必要が生じてきている。これは、いわゆるホ
ームオートメ−シラン等の要請から監視カメラやインタ
ーホン等の出力信号を高周波信号に変換して同一線路を
用いて伝、送するようになってきているからである。
By the way, the high frequency signal transmitted through the distribution circuit 1 has conventionally been set to include the FM broadcast or UHF broadcast band, that is, 76 to 770 MHz, but recently it has been set to include the HF band, 5 to 76 MHz. It has become necessary to also transmit signals such as This is because the output signals of surveillance cameras, intercoms, etc. are being converted into high-frequency signals and transmitted using the same line due to demands for so-called home automation systems.

しかしながら、分配回路1の伝送帯域を低域側にのばそ
うとすると、オートトランスT+のインピーダンスが減
少し、VSWRや分配損等の緒特性が悪化するという問
題が生じる。すなわち、オートトランスT、のインピー
ダンスが低下すると、インピーダンス変換が十分に行な
えなくなり、入力インピーダンスが低下して緒特性の悪
化につながるのである。このような問題を解決するには
オートトランスT、の巻数を多くすることが考えられる
が、その場合、高周波域において分配損が増大するとい
う問題が生じる。一般にUHF帯、VHF帯では、EI
AJ規格によれば、下表のような特性が要求されており
、HF帯でも同等の性能が要求される。
However, when trying to extend the transmission band of the distribution circuit 1 to the lower frequency side, the impedance of the autotransformer T+ decreases, causing a problem that characteristics such as VSWR and distribution loss deteriorate. That is, when the impedance of the autotransformer T decreases, impedance conversion cannot be performed sufficiently, and the input impedance decreases, leading to deterioration of the performance characteristics. A possible solution to this problem is to increase the number of turns of the autotransformer T, but in that case, the problem arises that the distribution loss increases in the high frequency range. Generally, in the UHF band and VHF band, EI
According to the AJ standard, the characteristics shown in the table below are required, and the same performance is required in the HF band.

[発明の目的] 本発明は上述の点に似みて為されたものであって、その
目的とするところは、周波数の低域におけるVSWRを
改善した分配器を提供することにある。
[Object of the Invention] The present invention has been made in a manner similar to the above points, and its object is to provide a distributor with improved VSWR in the low frequency range.

[発明の開示] (構成) 本発明に係る分配器は、高周波入力信号を複数の出力に
分配する分配回路と、分配回路の入力端および1つの出
力端にそれぞれ一端が接続された一対の直流阻止用のコ
ンデンサと、各コンデンサの他端間に接続された高周波
阻止用のチョークコイルとから成り、上記両コンデンサ
とチョークコイルとにより形成される並列共振回路の共
振周波数を分配回路の伝送周波数帯域の下限付近に設定
して成るものであり、伝送周波v!L領域の低域におけ
るVSWRを改善したものである。
[Disclosure of the Invention] (Structure) A distributor according to the present invention includes a distribution circuit that distributes a high-frequency input signal to a plurality of outputs, and a pair of direct current channels each having one end connected to an input end and one output end of the distribution circuit. Consisting of a blocking capacitor and a high frequency blocking choke coil connected between the other ends of each capacitor, the resonant frequency of the parallel resonant circuit formed by both capacitors and the choke coil is divided into the transmission frequency band of the distribution circuit. The transmission frequency is set near the lower limit of v! This improves the VSWR in the low range of the L region.

(実施例) 回路構成は基本的に従来と同様であって、第1図に示す
ように、入力信号を一対の出力に分配する分配回路1と
、分配回路1の入力端と一方の出力端とにそれぞれ挿入
された直流阻止用のコンデンサC,,C2と、コンデン
サC,,C2における分配回路1とは反対側の一端間に
接続された高周波阻止用のチョークコイルRFCとから
構成される。
(Example) The circuit configuration is basically the same as the conventional one, and as shown in FIG. It consists of capacitors C, , C2 for direct current blocking inserted in the capacitors C, , C2, respectively, and a choke coil RFC for blocking high frequency, connected between one end of the capacitors C, , C2 on the side opposite to the distribution circuit 1.

分配回路1は、入力側に設けられたインピーダンス整合
用のオートトランスT、と、オートトランスT、に立て
たタップに中間タップが接続された分配トランスT2と
、出力間のアイソレーションを保つために分配トランス
T2の出力端間に挿入された抵抗Rと、オートトランス
T、の一端とタップとの間に並列接続された位相補償用
のコンデンサC7とにより構成される。したがって、入
力端子■より入力された高周波信号はコンデンサCIを
通って分配回路1に入力され、オートトランスT1でイ
ンピーダンスが変換された後、分配トランスT2により
2分配されるのである。
The distribution circuit 1 consists of an autotransformer T provided on the input side for impedance matching, a distribution transformer T2 with an intermediate tap connected to a tap installed on the autotransformer T, and in order to maintain isolation between the output. It is composed of a resistor R inserted between the output ends of the distribution transformer T2, and a phase compensation capacitor C7 connected in parallel between one end of the autotransformer T and the tap. Therefore, the high frequency signal inputted from the input terminal (2) is inputted to the distribution circuit 1 through the capacitor CI, and after its impedance is converted by the autotransformer T1, it is divided into two by the distribution transformer T2.

ここにおいて、チョークコイルRFCとコンデンサC,
,C2とにより形成される共振回路を並列共振回路とみ
なし、その共振周波数を分配回路1の伝送周波数帯域の
下限付近に設定する。すなわち、コンデンサC,,C2
の容量をそれぞれC,、C2とし、チョークコイルRF
CのインダクタンスをLとすれば、共振周波数f0は、 で与えられる。しかるに、チョークコイルRFCのイン
ダクタンスを2.8μHとし、オートトランスT、およ
び分配トランスT2はコア(日本フェライト社製QMO
51)に巻線を巻装し、オートトランスT1の巻尾を1
:2、分配トランスT2は巻尾を1:1として、5MH
zと10MHzとでVSWRと分配損とについて測定し
たところ、第2図および第3図に示すような結果が得ら
れた。測定方法としては、第4図および第5図に示すよ
うに、ネットワークアナライザ2(ヒユーレットパラカ
ード社製8505A)を使用して、高周波電圧を分配器
Aに印加するとともに、その出力電圧を測定した。VS
WRは、分配器Aの入力端子■に高周波電圧を印加して
その反射電圧を測定することにより得られるのであって
、入出力電圧は方向性結合器3により分離した。また、
分配損は、入力端子工に高周波電圧を印加し、いずれか
一方の出力端子0、.02から出力電圧を取り出して測
定を行なった。すなわち、入力電圧をEis出力電圧を
Eoとし、Er” l Eo/E i lするとき、V
SWR=(1+Er)/(I  Er)分配損=−20
1oHEr として計算される。以上によりVSWRおよび分配損は
コンデンサC,,C2の容量が1000pF付近で最小
となるという知見かえられた。すなわち、上式によれば
、共振周波WLf o 物4 、2 M Hzとなるの
であり、伝送周波数の下限付近では共振周波数がその付
近に設定されているときに、VSWRと分配損とがほぼ
最小となった。
Here, choke coil RFC and capacitor C,
, C2 is regarded as a parallel resonant circuit, and its resonant frequency is set near the lower limit of the transmission frequency band of the distribution circuit 1. That is, capacitors C,,C2
Let the capacities of C, C2 be respectively, and choke coil RF
If the inductance of C is L, the resonance frequency f0 is given by: However, the inductance of the choke coil RFC is set to 2.8 μH, and the auto transformer T and distribution transformer T2 are equipped with cores (QMO manufactured by Nippon Ferrite Co., Ltd.).
51), and the winding tail of autotransformer T1 is 1.
:2, the distribution transformer T2 has a winding tail of 1:1, and is 5MH
When the VSWR and distribution loss were measured at 10 MHz and 10 MHz, the results shown in FIGS. 2 and 3 were obtained. As shown in Figures 4 and 5, the measurement method is to apply high frequency voltage to distributor A and measure its output voltage using network analyzer 2 (8505A manufactured by Hewlett Paracard). did. VS
WR is obtained by applying a high frequency voltage to the input terminal (2) of the distributor A and measuring the reflected voltage, and the input and output voltages are separated by the directional coupler 3. Also,
The distribution loss can be calculated by applying a high frequency voltage to the input terminals and applying a high frequency voltage to the output terminals 0, . The output voltage was taken out from 02 and measured. That is, when the input voltage is Eis and the output voltage is Eo, and Er'' l Eo/E i l, V
SWR=(1+Er)/(I Er) Distribution loss=-20
Calculated as 1oHER. As a result of the above, the knowledge that VSWR and distribution loss are minimized when the capacitance of capacitors C and C2 is around 1000 pF has been changed. In other words, according to the above equation, the resonant frequency WLf o is 2 MHz, and when the resonant frequency is set near the lower limit of the transmission frequency, the VSWR and distribution loss are almost minimum. It became.

[発明の効果] 本発明は上述のように、高周波入力信号を複数の出力に
分配する分配回路と、分配回路の入力端およ11つの出
力端にそれぞれ一端が接続された一対の直流阻止用のコ
ンデンサと、各コンデンサの他端間に接続された高周波
阻止用のチョークコイルとから成り、上記両コンデンサ
とチョークコイルとにより形成される並列共振回路の共
振周波数を分配回路の伝送周波数帯域の下限付近に設定
して成るものであり、伝送周波数帯域の下限付近でも入
力端子での整合がよくとれるようになるから、VSWR
を改善することができるという利点を有するものである
[Effects of the Invention] As described above, the present invention includes a distribution circuit that distributes a high-frequency input signal to a plurality of outputs, and a pair of DC blocking circuits each having one end connected to the input end and 11 output ends of the distribution circuit. and a choke coil for high frequency blocking connected between the other ends of each capacitor, and the resonant frequency of the parallel resonant circuit formed by the above capacitors and the choke coil is set to the lower limit of the transmission frequency band of the distribution circuit. The VSWR is set close to
This has the advantage of being able to improve the

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図、第2図および
第3図は同上の特性図、第4図および第5図は同上の測
定方法を示す概念図である。 1は分配回路、C3,C2はコンデンサ、RFCはチョ
ークコイルである。 代理人 弁理士 石 1)長 七 1・・・分配回路 C,、C,・・・コンデンサ 第1図 弔2図
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 and 3 are characteristic diagrams of the same, and FIGS. 4 and 5 are conceptual diagrams showing a measuring method of the same. 1 is a distribution circuit, C3 and C2 are capacitors, and RFC is a choke coil. Agent Patent Attorney Ishi 1) Chief 71...Distribution circuit C,,C,...Capacitor Diagram 1 Funeral Diagram 2

Claims (1)

【特許請求の範囲】[Claims] (1)高周波入力信号を複数の出力に分配する分配回路
と、分配回路の入力端および1つの出力端にそれぞれ一
端が接続された一対の直流阻止用のコンデンサと、各コ
ンデンサの他端間に接続された高周波阻止用のチョーク
コイルとから成り、上記両コンデンサとチョークコイル
とにより形成される並列共振回路の共振周波数を分配回
路の伝送周波数帯域の下限付近に設定して成ることを特
徴とする分配器。
(1) A distribution circuit that distributes a high-frequency input signal to multiple outputs, a pair of DC blocking capacitors with one end connected to the input terminal and one output terminal of the distribution circuit, and the other end of each capacitor. and a choke coil connected to the capacitor for high frequency blocking, and the resonant frequency of the parallel resonant circuit formed by the two capacitors and the choke coil is set near the lower limit of the transmission frequency band of the distribution circuit. Distributor.
JP28141286A 1986-11-26 1986-11-26 Distributer Pending JPS63135009A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28141286A JPS63135009A (en) 1986-11-26 1986-11-26 Distributer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28141286A JPS63135009A (en) 1986-11-26 1986-11-26 Distributer

Publications (1)

Publication Number Publication Date
JPS63135009A true JPS63135009A (en) 1988-06-07

Family

ID=17638795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28141286A Pending JPS63135009A (en) 1986-11-26 1986-11-26 Distributer

Country Status (1)

Country Link
JP (1) JPS63135009A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02306562A (en) * 1989-05-20 1990-12-19 Matsushita Electric Works Ltd Tv plug socket
JPH05244045A (en) * 1992-02-27 1993-09-21 Aiphone Co Ltd Distributor
JP2007067793A (en) * 2005-08-31 2007-03-15 Aiphone Co Ltd Television door phone apparatus
JP2007158665A (en) * 2005-12-05 2007-06-21 Nippon Antenna Co Ltd Distributor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02306562A (en) * 1989-05-20 1990-12-19 Matsushita Electric Works Ltd Tv plug socket
JPH05244045A (en) * 1992-02-27 1993-09-21 Aiphone Co Ltd Distributor
JP2007067793A (en) * 2005-08-31 2007-03-15 Aiphone Co Ltd Television door phone apparatus
JP4685555B2 (en) * 2005-08-31 2011-05-18 アイホン株式会社 TV door phone device
JP2007158665A (en) * 2005-12-05 2007-06-21 Nippon Antenna Co Ltd Distributor

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