JPS6313481A - Emphasis circuit - Google Patents

Abstract

PURPOSE:To decrease the amount of emphasis in a stage of pneemphasis at a time when a large amplitude signal is inputted by providing a circuit to multipy an amplitude-limited signal with a second coefficient and to subtract the product from an input video signal. CONSTITUTION:An input signal a1 is supplied to a high-pass filter 9 via a substractor 7 and is used as a signal c1, then amplitude-limited in a limiter 3 to come to be a signal d1. The signal d1 is multiplied by the coefficient K(smaller than one) in a coefficient circuit 8, supplied to the subtractor 7 where it is subtracted from the input signal a1, and goes to a signal b1. The signal d1 is multiplied by X(larger than one) in a coefficient circuit 4, then is added to the input signal a1 in an adder 5 and is used as a signal e1. Which is taken out from an output terminal 6. Since a loop made of the limiter 3 and the coefficient circuit 8 is thus provided, the transfer fuction GL of the limiter 3 gradually approaches zero at a time when a large-amplitude signal is inputted, and its response becomes quicker. As a result, at the said time of large- amplitude signal inputting, the amount of emphasis of the system becomes smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an emphasis circuit, and for example, to a circuit for pre-emphasizing and de-emphasizing a video signal in a VTR or the like.

Conventional technology When recording and reproducing video signals in a VTR, the SN
In addition to the main emphasis circuit, a non-linear emphasis circuit is used to improve the ratio.

FIG. 10 shows a block diagram of an example of a conventional nonlinear pre-emphasis circuit. The input video signal aO (FIG. 11(A)) entering terminal 1 has a time constant T. =RoCo
After the high-acid component is extracted by the high-pass filter 2, which is composed of an RC circuit (low-pass filter) and a subtracter, the S width is limited by the limiter 3, and multiplied by a coefficient X by the coefficient circuit 4. .

This signal multiplied by X and taken out is added to the original input signal aO in an adder 5 to produce a signal. ((B) in the same figure)
It is taken out from the output terminal 6. Note that in FIG. 3B, the broken line indicates the waveform when the limiter 3 is not provided.

In this case, when the amplitude of the input signal aO is large, the limiter 3 operates, so the emphasis is small as shown by the solid line in Figure (B), and when the amplitude of the input signal aO is small, the limiter 3 operates. Since it does not operate, the emphasis m becomes X, and the frequency characteristics in each case are as shown in FIG. By using a non-linear emphasis circuit, the edge portion of the signal is less likely to be cut off in the white/dark clip circuit at the subsequent stage, and the emphasis concavity can be increased and the S/N ratio can be improved.

Problems to be Solved by the Invention In the conventional circuit described above, the time constant of the circuit is the input signal a. is constant regardless of the magnitude of the amplitude, so when a large amplitude is input, the period in which the limiter is in operation becomes longer, and the frequency characteristics in the middle range increase in particular. As a result, there is a problem in that the high frequency range is further enhanced by the main pre-emphasis circuit at the subsequent stage, and the waveform is largely lost by the clipping circuit.

In addition, since the time constant is constant on the playback side, the clipping period in the clipping circuit becomes longer when inputting a large amplitude, and the SN ratio improvement effect cannot be obtained during the clipping period. There was a problem that noise remained immediately after the edge.

In pre-emphasis, the amount of pre-emphasis in the mid-range can be suppressed to a small level when inputting a large amplitude, and waveform loss due to the clip circuit in the subsequent stage can be suppressed to a small level.On the other hand, in de-emphasis, edge noise can be reduced when inputting a large amplitude. It is an object of the present invention to provide an emphasis circuit that thickens the effect.

Means for Solving the Problems The circuit of the present invention, as shown in FIG. A circuit (limiter 3, coefficient circuit 4, adder 5) that multiplies the amplitude-limited signal and adds it to the input video signal and outputs it as an emphasis output, and a circuit that multiplies the amplitude-limited signal by a second coefficient and adds it to the input video signal to output the input video A circuit that subtracts it from the signal and supplies it to the high frequency component extraction circuit (
A coefficient circuit 8 and a subtracter 7) are provided.

When inputting a large action amplitude, the transfer function GL of the limiter 3 approaches zero, the response of the system becomes faster, the period in which the limiter 3 is operating becomes shorter, and the emphasis wave becomes smaller. , when inputting a large amplitude, the mid-range frequency characteristics are made smaller. 'i! .

Waveform loss due to the clipping circuit can be suppressed to a small level, and in de-emphasis, the period with low de-emphasis darkness can be shortened, so the effect of reducing large-amplitude edge noise is large.

Embodiment FIG. 1 shows a block system diagram of a first embodiment (pre-emphasis circuit) of the circuit of the present invention, in which the same components as in FIG. 10 are given the same numbers. The input signal a+ (Fig. 2 (A)) that enters the terminal 1 is passed through a subtracter 7 (described later) to a high-pass filter consisting of an RC circuit (low-pass filter) with time constant T=RC and a subtracter. (High-frequency component extracting circuit) 9 to form a signal C+ ((C) in the same figure), and the amplitude is limited by a limiter 3 to form a signal d+ ((D) in the same figure).

The signal d1 is multiplied by a coefficient K (x1) by the coefficient circuit 8, and is supplied to the σ reducer 7, where it is subtracted from the input signal a1 to produce a signal b+.
((B) in the same figure). The signal d1 is multiplied by X (>1) in the coefficient circuit 4, and then added to the input signal al in the adder 5 to form a signal e+ ((E) in the figure), which is taken out from the output terminal 6. In addition, in Fig. 2, the broken line indicates limiter 3.
The waveform is shown without.

Here, the transfer function of the entire system is H(s>, limiter 3
The transfer function of GL (if the input signal a1 has a large amplitude, GL
→0. When the input signal a1 has a small amplitude, approximately expressed as GL→1), the frequency characteristic becomes as shown in FIG.

In this case, in order to obtain the same emphasis effect as shown in FIG. 10 when inputting a small amplitude, the time constant T of the RC circuit of the high-pass filter 9 must be
may be set to (1K)To. In this embodiment, a loop of the limiter 3 and the coefficient circuit 8 is provided, so when a large amplitude input is applied, the transfer function GL of the limiter 3 gradually approaches zero, and as a result, the time constant of the system becomes equal to that of the RC circuit. The time constant RC approaches the time constant RC and becomes (1-K> times the time constant when inputting a small amplitude, resulting in a faster response. Therefore, when inputting a large amplitude,
The period during which the limiter 3 is in operation becomes shorter, and the emphasis of the system becomes smaller.

Therefore, when inputting a large amplitude, the frequency response in the mid-range in particular does not increase as compared to the conventional circuit shown in Fig. Waveform loss can be suppressed to a smaller level than in conventional circuits.

FIG. 4 shows a second embodiment of the circuit of the present invention (pre-emphasis/
1 shows a block system diagram of a de-emphasis circuit (de-emphasis circuit), in which the same components as in FIG. 1 are given the same numbers and their explanations will be omitted. When operating as a pre-emphasis circuit, the switch S is connected to the terminal P side. In the figure, if the transfer function of the circuit surrounded by the dashed-dotted line is G (s),
This pre-emphasis circuit is a circuit shown in FIG. 5 (A>), and the transfer function of the entire system is 1+G(s). In this case, the output is taken out from the terminal 6P.

On the other hand, when operating as a de-emphasis circuit, the switch S is connected to the terminal side. In this case, coefficient circuit 4
The output signal is supplied to the subtracter 10 via the switch S, and is subtracted by 'g' from the original input signal. This subtracted output is taken out from terminal 6D as a high-frequency attenuated signal. This de-emphasis circuit becomes the circuit shown in Figure 5 (B),
The transfer function of the entire system is 1/(1+G(s)),
A de-emphasis circuit having complementarity with a pre-emphasis circuit can be obtained.

This also has a fast response of the entire system when inputting a large amplitude, so the period during which limiter 3 is operating is shortened, and as a result,
Since the time during which de-emphasis is clipped in the subsequent clip circuit is also shortened (the period of low de-emphasis is also shortened), the effect of reducing large-amplitude edge noise is greater than in the conventional circuit.

FIG. 6 shows a block diagram of a third embodiment of the circuit of the present invention. In this case, since the output of the limiter 31 is multiplied by X in the coefficient circuit 4, the overshoot becomes large, so the limiter 32 limits this overshoot, and its frequency characteristics are as shown in FIG. be. Other basic operations are the same as in each of the above embodiments, so
The explanation will be omitted.

FIG. 8 shows a block diagram of a fourth embodiment of the circuit of the present invention. This circuit consists of a high-pass filter 11 in place of the CR circuit and subtracter in each of the above embodiments,
The coefficient of the coefficient circuit 12 is (1+K)X,
Its frequency characteristics are as shown in FIG. This may constitute one less subtractor.

The present applicant previously disclosed in Japanese Patent Application No. 60-59098 (title of the invention "Luminance signal reproducing device and recording/reproducing device") a delay circuit that delays a luminance signal by a minute amount of 1H or less as a high-pass filter; Although a circuit consisting of a subtracter that subtracts the output signal of this delay circuit from the input luminance signal is used, even if the RC circuit of the high-pass filter 9 in the present invention is configured with the delay circuit described above, the same result as in each of the above embodiments will be obtained. effect can be obtained.

Effects of the Invention According to the circuit of the present invention, when a large amplitude input is applied, the response of the system becomes faster and the period during which the limiter operates is shortened. can be made smaller, the waveform loss due to the clip circuit can be suppressed to a small level, and even in de-emphasis, the period required for the limiter is shortened, so it is possible to expect a noise reduction effect immediately after a large amplitude edge. ! Since it is a JIP, it has a 1S length suitable for IC implementation.

[Brief explanation of drawings]

1 and 2 are block diagrams and signal waveform diagrams of the first embodiment of the circuit of the present invention, respectively, FIG. 3 is a frequency characteristic diagram of the circuit shown in FIG. 1, and FIGS. 4 and 5 are respectively The block system diagram and its equivalent circuit diagram of the second embodiment of the circuit of the present invention, FIGS. 6 and 7 are respectively the block system diagram and its frequency characteristic diagram of the third embodiment of the circuit of the present invention, and FIGS. 9 is a block system diagram and its frequency characteristic diagram of the fourth embodiment of the circuit of the present invention, FIGS. 10 and 11 are respectively a block system diagram and its signal waveform diagram of an example of a conventional circuit, and FIG. 12 is a diagram of its frequency characteristics. 10 is a frequency characteristic diagram of the circuit shown in FIG. 1...Video signal input terminal, 3.3+, 32...
Limiter, 4, 8.12...Coefficient circuit, 5...Adder, 6.6p, 6o...Output terminal, 7.10...Subtractor, 9.11...High-pass filter. Figure 1 Figure 2 Figure 3 Figure 8 Figure 1 Figure 12

Claims (4)

[Claims] (1) A high-frequency component extraction circuit that extracts the high-frequency components of the input video signal; and after limiting the amplitude of the output of the high-frequency component extraction circuit, it is multiplied by a first coefficient and added to the input video signal to output emphasis. The emphasis circuit further comprises a circuit that multiplies the amplitude-limited signal by a second coefficient, subtracts it from the input video signal, and supplies the result to the high-frequency component extraction circuit. emphasis circuit. (2) The high-frequency component extraction circuit comprises a low-pass filter and a circuit for subtracting the output of the low-pass filter from the input video signal.
Emphasis circuit described in section. (3) The emphasis circuit according to claim 2, wherein the low-pass filter is constituted by a delay circuit that delays the input video signal by a minute amount of 1H or less. (4) The emphasis circuit according to claim 1, wherein the high-frequency component extraction circuit is constituted by one high-pass filter.