JPS6313367A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce mutual intervention among cells and a soft-error by forming a base body in three layer structure of low concentration, high concentration and low concentration and shaping a trench type capacitance into a high concentration region in a semiconductor memory device with the trench type capacitance and a switching transistor. CONSTITUTION:A high-concentration impurity region 1 having the same conductivity type and a P type up to depth in depth Xp from the surface is formed onto a P-type semiconductor substrate region 2 as a P-type low-concentration semiconductor region, and a P-type low-concentration impurity region 3 is shaped similarly onto the region 1. Trench type capacitances 10 storing information signals in the shape of charges are formed by digging trenches 11, and are Xt deep. The trenches 11 penetrate the low-concentration impurity region 3, and do not reach up to the semiconductor substarte region 2, and the greater part is surrounded by the high-concentration impurity region 1. N-type impurity regions 21, 22 as source-drain regions are shaped in the low-concentration impurity region 3 in a switching transistor 20, thus realizing desired Vth (threshold voltage).

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a semiconductor memory device such as a DRAM (DRAM) having a trench type capacitor and a switching transistor.

B9 Summary of the Invention The present invention provides a semiconductor memory device having a trench capacitor and a switching transistor, in which the substrate has a three-layer structure of low concentration, high concentration, and low concentration, and the trench capacitor is formed in a high concentration region. , which aims to reduce mutual interference between cells and soft errors.

C1 Prior Art In semiconductor memory devices such as DRAMs, memory devices having a trench-type capacitor structure have been researched and developed due to demands for higher integration.

Such a semiconductor memory device involves digging a groove to a predetermined depth in a semiconductor substrate, forming a dielectric layer such as a silicon oxide layer in the groove, and further forming an electrode layer on the dielectric layer. A trench type capacitor is configured, and a switching transistor that turns on and off based on a selection signal such as a word line is mounted on the same substrate.
They have a structure in which they are formed adjacently within the same cell.

Reading and writing of information signals is performed by charging and discharging charges accumulated at the interface of the dielectric layer and the like via the switching transistor.

D0 Problems to be Solved by the Invention However, even in a semiconductor memory device having a trench type capacitor as described above, problems will arise if the degree of integration is further improved. .

That is, the above-mentioned trench capacitance is formed in a semiconductor substrate for each of a plurality of cells, but when the degree of integration is improved and the distance between the cells becomes close, there is a risk that the depletion layer will expand and a punch-through phenomenon will occur. Yes. This obstructs higher integration of semiconductor memory devices.

Additionally, if electrons are injected into such a trench capacitor due to the influence of alpha rays, etc., this will appear as a soft error,
There is a need to reduce such soft errors.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a semiconductor memory device that reduces mutual interference between cells and soft errors.

Means for Solving the E0 Problem The present invention provides a semiconductor memory device having a trench type capacitor and a switching transistor, in which a high concentration impurity region is formed on a low concentration semiconductor region, and a low concentration impurity region is formed on a liquid high concentration impurity region. The above problem is solved by a semiconductor memory device characterized in that the groove type capacitor is formed in the high concentration impurity region and is formed isolated from the low concentration semiconductor region.

F0 effect In the semiconductor memory device of the present invention, a trench type capacitor is formed in a high concentration impurity region, and in the liquid high concentration impurity region, the expansion of the depletion layer is suppressed, and mutual interference between cells can be prevented. . Further, since the high concentration impurity region functions as a barrier against α rays, soft errors can be reduced.

G. Example Preferred embodiments of the present invention will be described with reference to the drawings.

In the semiconductor memory device having the trench type capacitor and the switching transistor of this embodiment, since the high concentration impurity region and the low concentration impurity region are sequentially formed on the low concentration semiconductor region, mutual interference between cells can be suppressed. Soft errors can be reduced.

First, as shown in FIG. 1, the semiconductor memory device of this embodiment has a P-type semiconductor substrate region 2 as a P-type low concentration semiconductor region having the same conductivity type and a depth xp from the surface.
A P-type high-concentration impurity region 1 is formed to a depth of , and a P-type low-concentration impurity region 3 is further formed thereon. The impurity concentration of each of these regions 2, 1.3 has a distribution as shown in FIG. 2, for example, and the impurity concentration of the P-type semiconductor substrate region 2 is about 1015, The impurity concentration in region l is 10
17 to 1018 (c114), and the impurity concentration of the low concentration impurity region 3 is about 1016. still,
FIG. 2 shows the impurity concentration distribution in a cross section taken along the line A--A in FIG.

In the semiconductor memory device of the present invention, a trench type capacitor 110 and a switching transistor 20 are formed on a substrate having such an impurity concentration distribution. The trench capacitor 10, which stores information signals in the form of charges, is formed by digging an ill, and has a depth of Xt. This trench 11 penetrates the low concentration impurity region 3 and extends through the semiconductor substrate region 2.
Most of the area is surrounded by the high concentration impurity region 1. Therefore, as will be described later, mutual interference between cells can be prevented and soft errors can be reduced.

N-type impurities are introduced into the sidewalls and bottom of the all to form one lower electrode region 12 for each cell, a dielectric layer 13 is formed along the lower electrode region 12, and a dielectric layer 13 is formed as a plate electrode. A functional upper electrode region 14 is formed. Further, this capacitance tJljll is filled with the second polycrystalline silicon layer 15.

In the switching transistor 20, N-type impurity regions 21 and 22, which serve as source and drain regions, are formed in the lightly doped region 3, and a channel is also formed in the lightly doped region 3 to achieve a desired Vth (dark value). Voltage)
can be realized. A gate 1! is formed on the region where the channel is to be formed, with a gate oxide film 23 interposed therebetween. A pole 24 is formed. The impurity region 21 is connected, for example, to the lower electrode region 12 of the capacitor, and the impurity region 22 is connected to, for example, an A1 wiring 25 such as a bit line via a contact hole 26. Note that this contact hole 26 is opened through a glabellar insulation r527 such as As5G or BSG, and the gate electrode 24 may be made of polycide or silicide. Furthermore, when forming the Al wiring 25, the metal barrier N2
8 may be formed.

Capacitor 10 and switching transistor 20 as above
In each cell of a semiconductor memory device, a field oxide film 30 is formed, and a channel stopper region 31 is further formed, as in conventional DRAMs, to suppress channel formation between cells. . However, as devices become more highly integrated, even if the conventional field oxide film 30 and channel stopper region 31 do not provide sufficient device isolation, the semiconductor memory device of the present embodiment can provide isolation between cells. Interference can be effectively prevented. That is, the capacitance 1o is mostly surrounded by the high concentration impurity region 1, and this capacitance l.

The expansion of the depletion layer from the lower electrode region 12 is suppressed due to its high concentration, and phenomena such as chanch-through, which reduces the current dependence of the capacitance value, are prevented. Therefore, mutual interference between adjacent cells is suppressed, resulting in a semiconductor memory device with high performance.

Further, the semiconductor memory device of this embodiment has the impurity concentration distribution as described above, and even when α rays are incident on the semiconductor memory device from the substrate direction, the semiconductor substrate region 2 and the Since there is a difference in potential between the high concentration impurity region 1 and the high concentration impurity region 1, and the life of carriers can be shortened, the life of electron carriers caused by α rays can be shortened and injection into the capacitance region etc. can be suppressed. The probability of soft errors occurring can be reduced. moreover,
This high concentration impurity region 2 is a switching transistor 2
It will also function as a kW to 0.

In order to form an impurity concentration distribution that suppresses interference between cells of such a semiconductor memory device and prevents the adverse effects of alpha rays, it is necessary to form such an impurity distribution by high-energy ion implantation. can. Depending on the ion implantation, it is possible to achieve good controllability and reduce manufacturing costs. Ion implantation may be performed multiple times, or may be performed by epitaxial growth or in combination with epitaxial growth. In this way, the impurity concentration distribution formed by, for example, high-energy ion implantation is not specifically assigned to the distribution shown in FIG.
It goes without saying that the impurity concentrations of the upper low concentration impurity region 3 and the lower low concentration semiconductor region 2 of the semiconductor substrate region 2 may be approximately the same.

Such a semiconductor memory device can be accompanied by a peripheral circuit having a structure as shown in FIG. Third
The figure shows an example of the structure of a CMO3) transistor, which has a so-called twin well structure. Impurity regions 42 and 43 are formed in the P well region 41, and a gate oxide film 44 is further formed.
A gate electrode 45 is formed through the gate electrode 45, and an AN wiring 47 is formed through an opening in the glabella insulating layer 46 to operate as an NMOS transistor. Further, impurity regions 52 and 53 are formed in the N well region 51, and a gate electrode 55 is further formed via the gate oxide film 44, and the glabella insulating layer 46 is opened to form an A7! A wiring 47 is formed and the PMO3) operates as a transistor. Then, the impurity regions 42, 43.
52, 53, gate oxide film 44, interlayer insulating layer 46, Al
The wiring 47 and the like can be formed simultaneously on the same substrate together with the switching transistors of the above-mentioned DRAM cell, and the above-mentioned impurities are used to prevent launch-up and alpha rays in such peripheral circuit elements. Concentration distribution works.

Between these well regions 41 and 51, a channel stopper region 62 is formed under the field oxide film 61.
However, in this example, a high concentration impurity region 1 is formed at a deep position of about 1 to 2 μm, and this is 0MO3.
) Contributes to prevention of transistor latch amplifier. Further, since there is the high concentration impurity region 1, even when α rays are incident from the direction of the substrate, the lifetime of carriers can be shortened and the probability of soft errors occurring can be reduced. Therefore, even if a CMOS transistor is used as a semiconductor memory device, for example, in the peripheral circuit, there will be no adverse effects such as rough drop, soft errors, etc., and these can be done simultaneously in the memory and the peripheral circuit by using the impurity concentration distribution as shown in Figure 2 above. can produce synergistic effects.

H. Effects of the Invention The semiconductor memory device of the present invention has the above-mentioned impurity concentration distribution, and since the expansion of the depletion layer is suppressed in the high concentration impurity region, mutual interference between cells can be prevented. Further, since the high concentration impurity region functions as a barrier against α rays, soft errors can be reduced. Furthermore, even when a CMO3I-transistor is formed in the peripheral circuit, the performance of the peripheral circuit can be improved at the same time.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing an example of the structure of a semiconductor memory device of the present invention, FIG. 2 is an impurity concentration distribution diagram showing the impurity concentration distribution in a cross section taken along line A-A in FIG. 1, and FIG. 1 is a schematic cross-sectional view showing an example of a peripheral circuit of a semiconductor memory device of the invention. 1... High concentration impurity region 52... Semiconductor substrate region (low concentration semiconductor region) 3...
・Low concentration impurity region 10...Trench type capacitor 11...Trench 12...Lower electrode region 20...Switching transistor Patent Applicant Sony Corporation Representative Patent Attorney Kobu Mima Sakae Tamura - CMO5Tr 49'J Figure 3

Claims (1)

[Scope of Claim] A semiconductor memory device having a trench type capacitor and a switching transistor, wherein a high concentration impurity region is formed on a low concentration semiconductor region, a low concentration impurity region is formed on the high concentration impurity region, and the trench A semiconductor memory device characterized in that a type capacitor is formed in the high concentration impurity region and isolated from the low concentration semiconductor region.