JPS63132523A - Integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates generally to integrated circuits, and more particularly to an apparatus and method for reducing the feedback effects of output voltage spikes. be.

BACKGROUND OF THE INVENTION Advances in integrated circuit technology have resulted in tremendous improvements in the operating speed of integrated circuits, ie, the time it takes for circuit outputs to react in response to new inputs. As integrated circuit speed increases, output voltage rise and fall times also become faster. Similarly, fast rises and falls in the output voltage result in abrupt transitions in the output current.

Although faster operation is highly desirable, a significant problem arises from the abrupt transitions in output current.

The package holding the circuit has metal leads for interconnection of devices on the circuit board. Each lead has a small inductance associated with it. The leads are connected to the integrated circuit using bonding wires. This bonding wire also has an inductance attached to it. The voltage is determined by the product of inductance and the time rate of change of current, as expressed by the formula E=L-dI/dt. In this equation, L is a term related to inductance, and dl/dt represents a change in current over time. Due to sudden transitions in the output current,
This creates a large 1 meter change in the ground and 'Rh supply leads and bonding wires, resulting in voltage spikes in the ground and power supply leads. These voltage spikes affect the output voltage of the device, causing output ringing, ground bounce, and erroneous signals.

Since the power supply node and the ground node are used as voltage references in integrated circuits, the changes caused by the inductive voltages at the power supply node and the ground node will affect the integrated circuit. influence the signal within. For example, if the voltage level at the ground node increases, the human input signal will appear to decrease. Thus, if a slowly rising input signal rises above a voltage threshold, the resulting inductive voltage at the ground node will equivalently reduce the input signal voltage. Such phenomena generate erroneous signals and also cause disturbances within the integrated circuit.

To counter voltage fluctuations in the input signal due to inductive voltages, conventional circuits use hysteresis. In these circuits, the input signal has a voltage range, and within that range, even if it fluctuates, it will not be seen as an anti-radial signal. However, in high speed operating circuits, the inductive voltages at the power supply node and the ground node can easily exceed reasonable voltage ranges.

From the foregoing, it should be clear that there is a need for a method to prevent the propagation of erroneous input signals caused by inductive voltages present at the power supply node and the ground node.

SUMMARY OF THE INVENTION In accordance with the present invention, propagation of erroneous signals caused by inductive voltages present between the power supply node and the ground node of an integrated circuit is inhibited by latching the input signal until the induced voltage subsides. An integrated circuit is obtained.

According to another aspect of the invention, an output circuit is provided having an input stage, an output stage, an intermediate stage, and a latch circuit.

A latching circuit operates for a predetermined period of time until the inductive voltage present at the power supply node and the ground node dissipates.
The input of the intermediate stage is held at a predetermined voltage level.

In yet another aspect of the invention, the latch circuit provides a predetermined voltage level to the input of the intermediate stage after detecting a voltage change in the circuit.

In another aspect of the invention, the predetermined voltage is removed from the input of the intermediate stage after a second voltage change is detected in the circuit.

In another important aspect of the invention, the time period during which the latch circuit supplies the predetermined voltage to the input of the intermediate stage is
This can be changed by increasing or decreasing the number of delay elements associated with the latch circuit.

In order to more fully understand the invention, along with its advantages,
A detailed explanation will be given below with reference to the drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the invention can best be understood by referring to FIG. 1 of the drawings. Similar or corresponding elements are provided with the same reference numerals throughout the drawings. FIG. 1 shows a circuit used to prevent oscillations in the inverting output stage by momentarily latching the input to the proper state until the power supply line spike dissipates.

The CMO8 inverting stage is commonly referred to by the reference number 1o. An input 12 is coupled to a first forward inverting stage 14 . The first forward inversion stage 14 is coupled to a second forward inversion stage 16 which in turn is coupled to a third forward inversion stage 18. The third forward inverting stage 18 is coupled to a non-inverting stage 20. Non-inverting stage 2
0 provides the output 22 of the circuit. Capacitor 24 is equivalent to the capacitance of the circuit connected to this output.

The output 22 is coupled to three feedback inverting stages 28, 30, 32. The second feedback inversion stage 30 also includes a first P-channel transistor 34 and a first N-channel transistor 3.
It is connected to Gate 6. The sources of the first P-channel transistor 34 and the first N-channel transistor 36 are coupled to a node between the second forward-inverting stage 16 and the third forward-inverting stage 18. First P-channel transistor 3
The drain of P-channel transistor 4 is connected to the drain of second P-channel transistor 38 and the gate of third P-channel transistor 40 . The drain of first N-channel transistor 36 is coupled to the drain of second N-channel transistor 42 and the gate of third N-channel transistor 44 . a second P-channel transistor 38 and a second P-channel transistor 38;
The gate of the N-channel transistor 42 is coupled to the output of the third feedback inversion stage 32. The sources of second P-channel transistor 38 and second N-channel transistor 42 are coupled to vcc and ground node 46, respectively. Similarly, the third P-channel transistor 40 and the third
The sources of the N-channel transistors 44 are connected to the ground node 46, respectively. Third P-channel transistor 40 and third N-channel transistor 44
The drain of is connected to the input of the second forward inverting stage 16.

As is known, in a P-channel transistor, conduction occurs between the source and the drain when the gate voltage becomes negative with respect to the source voltage. Therefore, if the source is fixed at vcc, a P-channel transistor will conduct while a "low" signal is present on its gate, and will conduct while a "high" signal is present on its gate. do not. Conversely, in an N-channel transistor, conduction occurs between the source and drain when the gate voltage is positive with respect to the source voltage.

Therefore, if the source voltage of an N-channel transistor is fixed to ground, it will conduct when a "high level" signal is present on its gate, and will not conduct when a "low level" signal is present on its gate. . The transistor is
It is "turned on" when it is conducting (low impedance) and it is non-conducting (m impedance).
If it is in the state, it is "turned off".

In operation, the input receives input from another integrated circuit or from another stage of the same integrated circuit. The first forward inverting stage 14 holds its output voltage level until the input reaches the threshold voltage level. Assuming that the input signal transitions from low to high, the slowly rising signal present at input 12 is inverted by first forward inverting stage 14 after reaching a voltage threshold (this voltage threshold is is the level at which the forward inverting stage 14 considers the input to be a "high level" signal). This creates a low level signal at the output of the first forward inverting stage 14. This signal is inverted again by the second forward inverting stage 16, producing a high signal at the output of the second forward inverting stage 16. A third forward inverting stage 18 inverts this signal once more, producing a low signal at its output. After passing through the forward inverting stage 20, a low signal appears at the output 22 as the inverse of the signal present at the input 12.

When the output 22 changes from a high signal to a low signal, the charge stored in the output circuit capacitor flows to the ground node 46 and an inductive voltage appears at the ground node 46. When multiple outputs switch simultaneously, the current through ground node 46 increases proportionally, creating a larger inductive voltage at ground node 46. Since ground node 46 is the reference for all other voltages in this circuit, the voltage between input 12 and ground node 46 is reduced due to the inductive voltage present in ground node 46. If the inductive voltage present at ground node 46 exceeds the input voltage rise during the propagation of the signal from input 12 to output 22, a signal switching from high to low will appear at the input. This is called a false signal.

In circuits proposed so far, an erroneous signal can cause excavations in the circuit while it propagates from input to output. Since the input 12 voltage appears as a low signal to the first forward inverting stage 14, the first forward inverting stage 14 outputs a high signal in response to its recognized new input. Accordingly, a high signal appears at the output 22 after two successive inversions by the second and third forward inversion stages. At this point, the inductive voltage on ground node 46 reverses and the input signal again appears as a high signal, causing yet another change in the output signal. In fact, oscillations occur indefinitely in fast 0MO8 devices. However, if oscillation occurs even for a short period of time, the erroneous signal will make the device unreliable in most applications.

The present invention prevents such oscillations from occurring by momentarily latching the input until all dielectric voltage spikes from the power supply and ground nodes have dissipated. The operation of this circuit with respect to a low to high transition of the input signal is as follows. Prior to the input signal transition, the signal present at the input is low and the first forward inverting stage 14
the output signal of is high, the output signal of the second forward inverting stage 16 is low,
The output of third forward inverting stage 18 is high and the signal at output 22 is also high. The output signal of the first feedback inversion stage 28 is low;
The output signal of the second feedback inverting stage 30 is high and the output of the third feedback inverting stage 32 is low. Since the output signal of the second feedback inverting stage 30 is high, the first N-channel transistor 3
6 turns on. First N-channel transistor 3
6 is coupled to the output of the second forward inverting stage 16 so that the gate of the third N-channel transistor 44 is low, thus turning the third N-channel transistor 44 off. The second N-channel transistor 42 is also turned off because its gate is coupled to the output of the third feedback inverting stage 32.

When the output rises slowly and reaches the voltage threshold, the first
The forward inverting stage 14 recognizes the voltage present at input 12 as a high signal. A first forward inverting stage 14 inverts this high signal and produces a low signal at its output. This output becomes the input to the second forward inverting stage 16. A second forward inverting stage 16 inverts this low signal and produces a high signal at its output. Since the first N-channel transistor 36 is still turned on, it transfers the signal present at the output of the second forward-inverting stage 16 to the gate of the third N-channel transistor 44 .

Thus, when the voltage present at the output of the second forward-inverting stage 16 reaches the turn-on voltage of the third N-channel transistor 44, the third N-channel transistor 44 is switched from the ground node 46 to the first forward-inverting stage. 14 and pulls it down to a low level. The signal continues to propagate from the output of the second forward inverting stage 16 through the third forward inverting stage 18 and the forward inverting stage 20. Therefore, the signal is transferred to the second forward inverting stage 1
After appearing at output 6, it reaches output 22 with a delay of two gates.

Even if the switching output causes an inductive voltage to the ground node 46, the input to the second forward inverting stage 16 is not changed. This is because the third N-channel transistor 44 connects the input to the second forward inverting stage 16 to ground node 46. This causes the erroneous signal to become the first
is prevented from propagating through the forward inversion stage 14.

When the inductive voltage on ground node 46 dissipates, third N-channel transistor 44 must turn off in order to propagate a valid input signal from input 12 to output 22. In the present invention, the circuit is reset as follows. The low signal present at output 22 is passed through three feedback stages 28.
30.32 to provide sufficient gate delay for the inductive voltage at ground node 46 to dissipate. While the signal propagates through the feedback stage, the output of the second feedback inversion stage 30 switches from high to low, turning off the first N-channel transistor 36. Following this, the third
The output of the feedback inverting stage 32 switches from low to high, and the second
The third N-channel transistor 42 is turned on, and the third N-channel transistor 42 is turned on.
pulls down the gate of N-channel transistor 44 to a low level. At this point, third N-channel transistor 44 is turned off and second forward inverting stage 16 is ready to receive a new valid signal.

A similar circuit is also used to prevent inductive voltages from affecting the input voltage during high-to-low transitions. The operation of this circuit regarding the high to low transition of the input signal is as follows. Prior to the transition of the input signal, the signal present at the input is high, the output signal of the first forward-inverting stage 14 is low, the signal at the output of the second forward-inverting stage is high, and the signal present at the third forward-inverting stage 14 is low.
The signal at output 8 is low, and the signal at output 22 is also low. The signal at the output of the first feedback inversion stage 28 is high;
The signal at the output of the third feedback inverting stage 30 is low, and the signal at the output of the third feedback inverting stage 32 is high. Since the signal at the output of the second feedback inverting stage 30 is low, the first P-channel transistor 3
4 turns on. First P-channel transistor 3
Since the source of P-channel transistor 4 is connected to the output of second forward inverting stage 16, the gate of third P-channel transistor 40 is high, turning third P-channel transistor 40 off. The second P-channel transistor 38 is also turned off because its gate is coupled to the output of the third feedback inversion stage 32.

As the output falls slowly, the voltage threshold is reached and the first
The forward inverting stage 14 recognizes the voltage present at input 12 as a low signal. The first forward inverting stage 14 inverts the low signal to produce a high signal at its output.

This output becomes the input to the second forward inverting stage 16.

The second forward inverting stage 16 inverts the high signal to produce a low signal at its output. First P-channel transistor 34
Since is still turned on, it conducts and transfers the signal present at the output of the second forward inverting stage 16 to the gate of the third P-channel transistor 40. Thus, when the voltage present at the output of the second forward inverting stage 16 reaches the turn-on voltage of the third P-channel transistor 40, the third P-channel transistor 40 conducts and The output of stage 14 is connected to raise the high level. The input signal continues to propagate from the output of the second forward inverting stage 16 through the third forward inverting stage 18 and the forward inverting stage 20. The signal therefore reaches output 22 two gates later than it appears at the output of second forward inverting stage 16.

The third P-channel transistor 40 inverts the input to the second forward-inverting stage 16 even though the switching output causes an inductive voltage at node cC. Since it is pulled up to 0, the input to the second forward inverting stage 16 is not modified. This prevents erroneous signals from propagating through the first forward inverting stage 14.

In the present invention, the circuit is reset as follows.

The high signal present at output 22 is passed through the feedback stage 28°30 of 311.
．． 32, providing sufficient gate delay for the inductive voltage on the cc node to dissipate. While the signal propagates through the feedback stage, the output of the second feedback inversion stage 30 switches from low to high, turning off the first P-channel transistor 34. Thereafter, the output of the third feedback inversion stage 32 switches from high to low, turning on the second P-channel transistor 38 and pulling the gate of the third P-channel transistor 40 high. At this point, third P-channel transistor 40 is turned off and second forward inverting stage 16 is ready to receive a new valid signal.

The time interval during which input 12 is effectively removed from output 22 is
This can be done by changing the number of feedback stages or by changing the size of the feedback inverting stages to have a larger delay in each stage. In the embodiment shown, the delay element operates in response to voltage changes at the output 22, but with slight modification the delay element can be connected to other nodes in the circuit to achieve similar effects. .

The extension time used in a particular embodiment depends on the output F (the maximum frequency at which the output switches from a valid high signal to a valid low signal and from a valid low signal to a valid high signal) and the circuit. is determined by the conflict with the minimum allowable input rise and fall times. An error signal may occur when the potential difference between the input signal and the ground node 4-6 becomes less than a high voltage threshold limit. Therefore, longer latch times and therefore longer delays are required to accommodate slowly rising signals. However, since the output cannot be switched while the input is latched, the circuit's Flax must be reduced to accommodate more slowly rising signals. Many applications do not involve slowly rising signals, so a shorter latch time can be used to design the circuit.

It should be noted that erroneous signals can be generated by noise sources in the circuit other than inductive voltages at the power supply and ground nodes. The present invention provides that after a change in the input signal,
It is adapted to hold the input unchanged for a predetermined period of time, thus also preventing much of the unwanted noise from propagating through the circuit.

Additionally, although the embodiment shown here latches the input signal at the input to the second forward-inverting stage 16, modifications may be made to latch the input signal at other locations if desired. I would like to point out that it is possible.

FIG. 2 shows the invention used with a non-inverting output circuit. The non-inverting output circuit 48 is connected to the third sequential inverting stage 18
is removed and an additional feedback inversion stage, complementary feedback inversion stage 50, is added to provide the correct signals to transistors 38-44. Similar to 10.

Non-inverting output circuits also suffer from similar problems as inverting output circuits with respect to inductive voltages present at the power supply node and the ground node. In a non-inverting output circuit, a high to low transition at the input causes a high to low transition at the output. A high to low signal transition at the output generates a dielectric voltage on the ground node because the ground node resists the current change. This inductive voltage changes the reference point for the voltage in the circuit and the input signal becomes ostensibly lower. Since the input signal changes from high to low, no induced voltage is generated at the input signal. But when the current from the output circuit starts to decrease, the ground node resists the change in current, so
Ground boiling voltage behaves in the opposite way. This phenomenon is
known as "overshoot". The inductive voltage on the ground boil caused by the overshoot causes an increase in the voltage difference between the input signal and the ground node, and acts to make the input signal appear higher. If the input signal is greater than the high voltage threshold limit, an erroneous signal may be generated at the input.

As before, the invention prevents the propagation of erroneous signals through this circuit by latching onto a valid signal at the input to the second forward inverting stage. In operation, non-inverting output circuit 48 acts on high-to-low transitions of the input signal as follows.

Prior to a transition in the input signal, the signal present at the input is high, the signal at the output of the first forward-inverting stage 14 is low, the signal at the output of the second forward-inverting stage 16 is high, and the signal present at the output 22 is also high, the signal at the output of complementary feedback inverting stage 50 is low, the output of first feedback inverting stage 28 is high, the signal at the output of second feedback inverting stage 30 is low, First feedback inversion stage 32
The output is high. Since the signal at the output of second feedback inverting stage 30 is low, first P-channel transistor 34 turns on. Since the source of the first P-channel transistor 34 is coupled to the output of the second forward-inverting stage 16, the gate of the third P-channel transistor 40 is high, thus turning off the third P-channel transistor 40. . The second P-channel transistor 38 also has its gate connected to the output of the third feedback inverting stage 32 and is thus turned off.

As the output falls slowly, a voltage threshold is reached and the first forward inverting stage 14 recognizes the voltage present at the input 12 as a low signal. The first forward inverting stage 14 inverts this low signal and produces a high signal at its output, which is inverted by the second forward inverting stage 1.
This is the input to 6.

A second forward inverting stage 16 inverts this high signal to produce a low signal at its output. First P-channel transistor 3
4 is still turned on, so the second forward inverting stage 16
The signal present at the output of is transmitted to the gate of the third P-channel transistor 40. Thus, when the voltage present at the output of the second forward-inverting stage 16 reaches the turn-on voltage of the third P-channel transistor 40, the third P-channel transistor 40 conducts and changes vcc to the first forward-inverting voltage. It is transmitted to the output of stage 14 and raised to a high level. The input signal continues to propagate through the second forward inverting stage 16 and then through the forward inverting stage 20. Therefore, after the signal appears at the output of the second forward inverting stage 16, it reaches the output 22 with a delay of one gate.

Even if the overshoot of the switching output causes a dielectric voltage at the ground node, the third P-channel transistor 4
0 is the input to the second forward inverting stage 16 at V. . Because of the pull-up, the input to the second forward inverting stage 16 is not modified. This causes the error signal to be transferred to the first forward inverting stage 1.
4 is prevented from propagating through.

In the present invention, the circuit is reset as follows.

The low signal present at output 22 is passed through four feedback stages 50°28.
30.32, providing sufficient gate delay for the overshoot inductive voltage at ground node 46 to dissipate. While the signal propagates through the feedback stage, the output of the second feedback inverting stage 30 switches from low to high and the output of the first P
Channel transistor 34 is turned off. Subsequently, the output of the third feedback inversion stage 32 switches from high to low, turning on the second P-channel transistor 38 and pulling the gate of the third P-channel transistor 40 high. At this point, third P-channel transistor 40 is turned off and second forward inverting stage 16 is ready to receive a new valid signal.

Non-inverting output circuit 48 for input signal transition from low to ^
The operation of this will not be described here, but it will be easily beaten by the above explanation.

As mentioned above, the latch time can be adjusted as large as necessary to prevent false signals.

Again, the latch time increases F or
It is the designer's choice between accepting a slowly rising input ax signal.

The present invention thus provides the above-mentioned advantages in addition to numerous other advantages. As is clear to those skilled in the art,
The invention is susceptible to a wider range of modifications and variations. The scope of the invention is limited only by the claims.

[Technical Time 6511 One of the technical features of the present invention is that the erroneous signal caused by the inductive voltage spikes present at the power supply node and the ground node of the integrated circuit is suppressed until the inductive voltage sufficiently disappears. This is prevented by latching the signal until it is valid. Yet another technical feature is that the latch time of the present invention can be easily adjusted for use in many diverse applications.

Yet another technical feature of the invention is that the invention is applicable to both inverting and non-inverting output circuits. Yet another technical feature is that the circuit can be used with OMO8 and other transistor-based circuits.

Regarding the above description, the following sections are further disclosed.

(1) An integrated circuit having a power supply node and a ground node, an input stage for receiving an input signal, an output stage for transmitting an output signal, and an integrated circuit connected between the input stage and the output stage. , an intermediate stage for converting an input signal into a desired output signal, operative to hold the input of said intermediate stage at a predetermined voltage level for a predetermined time interval, the power supply node of the integrated circuit, the ground a latch circuit for making the output signal generally unaffected by fluctuations in the input signal caused by inductive voltages present at the node;
integrated circuits, including;

(2) The integrated circuit of paragraph 1, wherein the latch stage includes means for detecting a voltage change at a first node in the integrated circuit.

(3) The circuit of paragraph 2, wherein the latch stage is responsive to the voltage change in the first node to hold the input of the intermediate stage at the predetermined voltage level. Integrated circuits.

(4) The circuit of paragraph 3, wherein the latch stage maintains the predetermined voltage level by connecting a switch between the reference voltage source and the upper input to the intermediate stage. It became an integrated circuit.

(5) The integrated circuit of paragraph 2, wherein the latch stage includes means for detecting a voltage change at a second node in the integrated circuit.

(6) The integrated circuit of clause 5, wherein the latch stage disconnects the switch a predetermined time after detection of the voltage change at the second node.

(7) A circuit having a power supply node and a ground node, which includes an input stage for receiving a signal from an external signal source, an output stage for transmitting an output signal, and a circuit between the input stage and the output stage. a plurality of inverting and non-inverting stages disposed therebetween; a latch circuit for supplying a predetermined voltage for a predetermined time interval to a selected one of said inverting and non-inverting stages; a latch circuit operative to attenuate the propagation of erroneous signals due to yh's voltages on the power supply node and the ground voltage.

(8) The circuit of item 7, wherein the latch circuit is
A circuit adapted to supply said predetermined voltage to one of said inverting or non-inverting stages after detecting a first voltage change in the circuit.

(9) The circuit of clause 8, wherein the predetermined voltage is applied for a predetermined time interval after the second voltage change in the circuit.

(10) An output circuit comprising: an input stage for receiving an input signal, an output stage for transmitting an output signal, first and second stages arranged in series between the input stage and the output stage. a voltage detection device placed after said second inversion stage; a switching device placed between a predetermined voltage source and an input to said second inversion stage; a switching device operable to cause a current to flow between a voltage source and the input stage to the second inverting stage upon detection of a voltage change by a voltage sensing device, the switching device being installed between the output stage and the switching device; a stopping device for stopping the current between a predetermined voltage source and said input stage to the E2 second inverting stage after a predetermined time interval after a change in the output signal; an output circuit, including a stopping device operative to cause the output to stop;

(11) The output circuit of item 10, wherein the voltage sensing device is a first transistor having a source connected to the output of a second inverting stage and a drain connected to a switching device.

(12) The output circuit according to item 11, wherein the voltage detection device further includes a plurality of delay devices connected between the output stage and the first transistor.

(13) The output circuit of paragraph 10, wherein the switching device includes a second transistor, the second transistor having its source connected to the predetermined voltage source, and the train of the second transistor connected to the predetermined voltage source. an output circuit, such as coupled to an input to the second inverting stage;

(14) The output circuit according to item 13, wherein the second transistor has its gate connected to the voltage detection device.

(15) The output path of paragraph 10, wherein the stopping device includes a third transistor, the third transistor having its source coupled to the predetermined voltage source and switching its drain. Output circuit connected to the device.

(16) The output circuit of item 15, wherein the stopping device further includes a plurality of delay devices disposed between the output stage and the third transistor.

[Abstract 1 The output circuit 10 is a power supply node■. The propagation of erroneous signals caused by inductive voltages present at C and ground node 46 is prevented by latching the human input signal until the inductive voltages disappear. The inverting stage 28.30.32 predetermines the time interval during which the input signal is latched.

[Brief explanation of the drawing]

Figure 1 shows that the CM
Figure 3 shows a layout of the present invention used with an O8 inverting output stage. Figure 2 shows that the C
Figure 3 shows a layout of the present invention used with an MO8 non-inverting output stage. (Reference code) 10... CMO3 inversion stage 12... Input 14... First forward inversion stage 16... Second forward inversion stage 18... Third forward inversion stage 2o... Non-inverting stage 22... Output 24... Capacitor 28... Feedback inverting stage 3o... 32... 34... First P channel transistor 36... First N channel transistor 38... ...Second P-channel transistor 4o...Third P-channel transistor 42...Second N-channel transistor 44...
Third N-channel transistor 46...vcc and ground node 48...non-inverting output circuit 50...complementary feedback inverting stage

Claims (1)

[Claims] (1) An integrated circuit having a power supply node and a ground node, an input stage for receiving an input signal, an output stage for transmitting an output signal, and an integrated circuit connected between the input stage and the output stage. , an intermediate stage for converting an input signal into a desired output signal, operative to maintain the input of said intermediate stage at a predetermined voltage level for a predetermined time interval;
An integrated circuit comprising: a latch circuit for making said output signal generally unaffected by fluctuations in said input signal caused by inductive voltages present in a power supply node of the integrated circuit, a ground node.