JPS63132473A - Semiconductor rom cell - Google Patents

Abstract

PURPOSE:To establish coincidence between contents of a ROM and external data supplied from bit lines, by adding transistors and supplement lines (sense lines) to a ROM cell. CONSTITUTION:The title cell is provided with first transistors 1-7-1-10 and second transistors 1-11-1-14. The first transistors have supplement lines, i.e., sense lines 1-5 and 1-6 arranged apart from bit lines 1-1 and 1-2 and word lines 1-3 and 1-4. Their gate terminals are connected to the bit lines, and source terminals are connected to a reference voltage source. The gate terminals of the second transistors are connected to the word lines, and source terminals are connected to the supplement lines. The drain terminals are connected to the drain terminals of the first transistors and either one of the bit lines in the programmable manner. The information of the bit lines is detected by a sense circuit 1-20. The information concerning to whether coincidence is established or not is output from an address detection circuit 1-21 in accordance with contents of a ROM cell on the word lines and the information from the bit lines.

Description

[Detailed description of the invention] [Industrial application field] Misfire 8A relates to semiconductor ROM cells, particularly ROM
Write in cell′! The present invention relates to a semiconductor ROM cell having a function of matching the contents stored in the data with the data to be searched.

[Conventional technology]

Conventionally, in order to realize the function of matching the content written in the ROM cell with the information to be searched for, it was necessary to read the data written in the ROM cell by giving address data to the data ROM cell. In addition, a table/look amplifier ROM cell is required to supply data and output all address data, and data ROM can be used as needed.
Cell, table, and look amplifier ROM cell accesses were all switched and used. Such a data ROM cell circuit is shown in FIG. The operation of the data ROM cell circuit shown in FIG. 2 will be explained below.

In FIG. 2, 2-1, 2-2 are bit lines.

2-3.2-4 is a word line, and transistor 2-5
The gate terminals of M2-6 are connected to word line 2-3, and the upper gate terminals of transistors 2-7, 2-8 are connected to word line 2-4. Transistor 2-5.
The source terminal of 2-6.2-7.2-8 is connected to earth GND. Furthermore, transistor 2-5.2-6.
The drain terminals of transistors 2-7 and 2-8 can be connected to the bit line in a programmable manner, and in the example of FIG.
1°2-2, thereby connecting the RO
M cell 2-11. 2-14 is at '1# level.

The ROM cell 2-12.2-13 is in a state where "0#" is written.

To read the contents of ROM, address decoder 2-9
selects one of the word lines 2-3 and 2-4, turns on the transistor whose gate terminal is connected to the word line, and connects the bit line to earth GND through the turned-on transistor. The sensing circuit 2-10 detects whether or not this has been done.

[Problem that the invention seeks to solve]

Conventionally, in order to search all the contents written in such a data ROM cell circuit, address input data k + "j3'r D table of the data ROM cell circuit
Write it into the look amplifier ROM cell circuit.

This table lookup ROM cell circuit is used to obtain address data of data to be searched. Therefore, the table and
Not only is a lookup ROM cell circuit required, but also a data ROM cell circuit and a table lookup ROM
Each cell circuit requires an address decoder and a sense amplifier, which increases the area occupied by the semiconductor chip and the power consumption.

An object of the present invention is to match the data to be searched with the data ROM cell that is originally used and perfect for giving address data and retrieving data, and the contents written in the data ROM cell. Both the table and lookup ROM cell functions are realized in one ROM cell. No need to increase address decoders or sense circuits.
It is an object of the present invention to provide a semiconductor ROM cell that occupies a small area and consumes little power.

[Means for Resolving Problem 14] According to the present invention, in a semiconductor ROM cell (1-15) having a bit 'a (for example, 1-1) and a word line (for example, 1-3), Additional lines (i.e., sense lines 1-5) provided separately from the Z line and the word line
furthermore, a dart terminal is connected to the @marked bit line,
a first transistor (e.g., 1-11) having a source terminal connected to a reference voltage source (e.g., ground), a dart terminal connected to the word line, a source terminal connected to the additional line, and a drain terminal; a second transistor (1) programmably connected to either the drain terminal of the first transistor and the bit line;
-7) A semiconductor ROM cell having the following properties is obtained.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. 1st figure 2
This figure shows a content add-on ROM with a word x 2 bit configuration. In Figure 1, 1-1.1, -2 are bit lines, 1
-3.1-4 is a word line, -5,1-6 are sense lines, transistors 1-7.1-8.1-9.1-10
, each gate terminal is connected to bit line 1-1 or 1-2.

All source terminals are connected to earth GND.

Furthermore, transistors 1-11, 1-12, 1-13
゜■-14 has each gate terminal connected to the word line 1-
3 and 1-4, and its source terminal is connected to sense lines 1-5 and 1-6. Transistor □1-11.1
-14 drain terminals are bits Ml-1, 1-, respectively.
Connected to 2. a drain terminal of transistor 1-12 is connected to a drain terminal of transistor 1-8;
The drain terminal of transistors 1-13 is transistor 1
-9 is connected to the drain terminal. Here, the drain terminal of transistor 1-11.1-12.1-13.1-14 is connected to bit line 1-1 or 1-2, or transistor 1-7.1-8.1-9 Whether or not it is connected to the drain terminal of 1-10 can be switched by a specific wiring layer in the zologram sample. In the example of FIG. 1, 1" is written in ROM cells 1-15.
On is written '1'.

Next, the operation of the ROM shown in FIG. 1 will be explained. first,
A case will be described in which the entire contents of a ROM cell are extracted. At this time, the address detection circuit 1-21 senses i1. −
5.1-6 is a dropped toss to earth GND.

When word line 1-3 is selected by address decoder 1-19, transistor 1-11 is on, so current flows from bit line 1-1 to sense line 1-5 through transistor 1-1.1. However, since the transistor 1-14 is off, there is no current flowing from the pin 41-2 to the sense line 1-6. As a result, information of '1' is transmitted from bit line 1-1.
Information of 0'' can be detected from the bit line 1-2 by the sense circuit 1-20 connected to the bit line.

Next, data is input from bit line 1 ``''1 t 1-2, and 1. -15.1-16.1-17.1-18 The case of matching the contents of each ROM cell will be explained. When matching the contents of the ROM, all word lines 1-3゜1-4 are selected by the address decoder 1-19, and transistors 1-11゜1-12.1-13.1 are selected.
-14 are all turned on, and address detection circuits 1-2 are turned on.
1, the sense lines 1-5 and l-6 are precharged to the 1" level. The bit line buffer 1-20 and the content to be matched to the bit line, for example, the bit line 1-1.
When inputting the "1" level that matches the content of ROM cell 1-15 to bit line 1-2 and the 1101j level that matches the content of ROM cell 1-16 to bit line 1-2, ROM cell 1-
At 15, the bit line 1-1 is at the "1# level" and the sense line 11-5 is also at the "1" level, and the transistor 1-11 is on, so the sense line 1-5 is in the "1" V level state. Even in the 80M cell 1-16, where bit line 1-2 is at NO# level, transistor 1-
8 is turned off, and the sense line 1-5 maintains the "1 level" state, so the address detection circuit 1-21 detects information that there is a match.

On the other hand, in ROM cells 1-17, the bit line ]-1
is at the °′1” level, so transistors 1-9 f
t on, the transistor 1-13 is also on, so the sense line 1-6 is connected to GN through the transistor 1-9.1-13.
The bit line 1-2 in the ROM cell 1-18 is also at the ``0#'' level, so the bit line 1-2 is connected to the ``0'' level in the ROM cell 1-18. The level of sense 1l-6 is +11
Changes from 31 to 0#. Therefore, R on the word line
If there is even one mismatch between the contents of the OM cell and the information from the bit line.

The sense line transitions to the "0" level and mismatched information is detected by address detection port 1-21.

〔Effect of the invention〕

As explained above, in the present invention, by adding one transistor and an additional line (sense line) to a conventional ROM cell, it is possible to match the ROM contents with external data supplied from a bit line. A semiconductor ROM cell that occupies a small area and consumes less power can be provided without increasing address decoders or sense circuits that consume the most power.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor ROM cell according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional data ROM cell. 1-1 + 1-2 e 2-1. t 2-2...
bit line. 1-3.1-4.2-3.2-4...word line, 1-
5.1-6...Sense line, 1-7.1-8.1-9.
1-10.1-11.1-12.1-13゜1-14.
2-5.2-6.2-7.2-8...Tran Zosta, 1-15.1-16.1-17.1-18...ROM cell #2-112- of the present invention 12゜2-13.2-1
4... Conventional ROM cell, 1-19° 2-9... Address decoder, 1-20... Sense circuit/Pino l-
Line buffer, 2-10...Sense circuit. 1-21...Address detection circuit.

Claims (1)

[Claims] 1. A semiconductor ROM cell having a bit line and a word line, which has an additional line provided separately from the bit line and the word line, and further has a gate terminal connected to the bit line, and a reference voltage source. a first transistor having a source terminal connected to the drain terminal of the first transistor and the bit line; a gate terminal connected to the word line; a source terminal connected to the additional line; and a drain terminal connected to the drain terminal of the first transistor and the bit line. and a second transistor programmably connected to either one of the semiconductor ROM cells.