JPS63131662A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To improve blooming resistance and picture quality, by clamping a picture element SIT whose gate potential exceeds a prescribed potential in which no blooming is generated at the prescribed potential out of all of the picture elements SIT in a period other than a prescribed readout period. CONSTITUTION:Resetting MOSFETs 21-1-21-4 have functions to clamp the gate potential of the picture element SIT which exceeds the prescribed potential where the blooming is generated in a non-selection time other than to reset the picture element SIT. For example, when light beams with high intensity over a saturation light quantity projected on a non-selective picture element SIT 10-33, the gate potential is clamped at a threshold voltage in the forward direction of a gate/source diode. And no output appears until the gate voltage goes over the sum of a pinch-off voltage and the threshold voltage of a column line potential amplifying MOSFET18. In such way, the blooming resistance can be improved, and high picture quality can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a solid-state imaging device using a static induction transistor.

[Conventional technology]

Conventionally, solid-state imaging devices that use MO3I-transistors or charge-coupled devices such as CCDs and BBDs are common.

However, those using MOS) transistors have the drawbacks of weak output signals, poor signal-to-noise ratio, and low photosensitivity, and those using CCD, BBD, etc. There are drawbacks such as loss and difficulty in manufacturing.

As a solution to these drawbacks, for example, Japanese Patent Application Laid-open No. 58
A static induction transistor (StaticInducti) is installed in each pixel as disclosed in Japanese Patent No. 105672.
2. Description of the Related Art Solid-state imaging devices equipped with on-transistor (hereinafter referred to as SIT) have been proposed.

The present applicant has also developed various improved solid-state imaging devices equipped with the above-mentioned SIT, one example of which will be explained with reference to FIG.

FIG. 4A is a structural diagram of one pixel constituting a solid-state imaging device using SIT, and FIG. 4B is a circuit configuration diagram of the solid-state imaging device.

In Figure 4A, n acts as the drain of SIT.
3. On a silicon substrate 1, an n-epitaxial layer 2 which becomes a channel region is deposited.

A shallow n source region 3 is formed in this epitaxial layer 2, and this source region 3 is formed in the epitaxial layer 2.
It is surrounded by a p0 gate region 4 within. A MOS capacitor 5 is formed on the gate region 4, and a pulse is supplied via this capacitor 5. When the gate region 4 is reverse biased, a depletion layer is formed outside this gate region. When light enters the depletion layer and hole-electron pairs are generated, the electrons are swept out to the source 3 and drain regions 1, and the holes are accumulated in the gate region 4. Therefore, the gate potential increases, the current between the drain and the source is modulated by the voltage change, and a light-dependent amplified signal is obtained. In addition, the fourth
Reference numeral 6 in FIG. A is a separation area for separating each pixel.

In FIG. 4B, reference numerals 10-11.10-12. ---
--10-21, 10-22. −−−−−,−−−−−
, 10-44 are SITs constituting the pixels shown in FIG. 4A, and for convenience of explanation, these SIs are
An example is shown in which T's are arranged vertically and horizontally in 4 rows and 4 columns. Each source of vertically arranged SIT is connected to a column line 11-1.11-
2. ------11-4 are commonly connected, and these column lines are connected to the switch M constituting the horizontal selection switch.
O3FET13-1.13-2. ---Connected to video line 14 via 13-4. Switch M
Each gate of the OS FETs 13-1 to 13-4 is connected to the horizontal scanning circuit 15, and each gate receives horizontal scanning pulses φ and I.

φ3Z+---φ34 is added.

On the other hand, each gate of the SITs arranged horizontally is connected to the input terminals 12-1, 12-2, . ---12-4, and each of these row lines is connected to the vertical scanning circuit 16 and receives a vertical scanning pulse φG++φGZ.
＋ −−−−1φ. 4 is applied to the gates of the SITs arranged in the machine.

When a pixel row is selected by applying the vertical scanning pulse to the row line, and a pixel column is selected by the horizontal scanning pulse, the optical signal current of the pixel at the intersection is read out. In this way, by sequentially outputting horizontal and vertical scanning pulses, each pixel is sequentially scanned and a signal for one pixel is obtained.

- FIG. 5 is a signal waveform diagram showing the timing of pulses that operate the solid-state imaging device. Gate selection (vertical scanning) pulse φ. consists of pulses having two types of high levels 1 and vis, and takes the value of the read level VID during the horizontal scanning period of each line, and becomes the reset level V□ during the subsequent horizontal blanking period tllL. The source selection (horizontal scanning) pulse φ goes to a high level in each horizontal scanning period, and sequentially scans horizontally arranged pixels.

The reset pulse φ8 is a pulse that becomes high level in each horizontal blanking period, and performs a reset action on the pixels from which the signal is read.

Figure 6 shows the circuit configuration when focusing on one pixel SIT, where CGD is the parasitic capacitance between the gate and drain,
CCS is the parasitic capacitance between the gate and source, C8 is the stray capacitance of the source line, and ROM is the horizontal selection switch MO3
This is the on-resistance of FET'rs.

Figure 7 shows the pixel S when horizontal scanning pulse φ3, vertical scanning pulse φ6, and reset pulse φ are applied to pixel SIT.
It shows temporal changes in the gate potential (G) and source potential (2) of IT. Note that φ8 is a forward dark value voltage of a gate/source diode, which will be described later.

Hereinafter, with reference to FIGS. 5 to 7, gate potential (2) will be explained. , temporal changes in the source potential VS will be sequentially explained.

(1) At time t, when φG=V(〉φ, ), φ reaches the old gh level, the source potential ■, is reset to GND, and ■,=φ.

(2) Pulse φ depending on the time. , φ blades become GND, the gate potential 6 becomes a reverse bias state given by the following equation, and optical integration starts.

Here, CJ = Cas + Ca.

(3) At time t3, in the light integration time, the photocharge Q generated by light irradiation
, h are accumulated in the gate capacitance (CG+CJ). Above Q
Qt is given by the following equation.

Qoh= GL -A -P -t 50,
=GL-A-E------+21Here,
GL is the production rate (μ・8/μ−), A is the light-receiving surface area (el
l"), P is the light irradiance (μ-/cm"), Lin
L is the integration time (S), E is the exposure amount (E = P - ttf
it). From equations (1) and (2) above, the gate potential V becomes φc''V at time t4 (4). If Vc4>Vp, (where ■, is the pixel S
The drain current of the pixel SIT (which is the potential difference between the gate and source at which the drain current of TT begins to flow and is called a pinch-off voltage) flows and charges the source line capacitance C3.

This charging continues until the potential difference VGS between the gate and source reaches V. Therefore, the source potential is given by the following equation.

(2) Since P is rich in φ, almost no current flows from the p''' gate to the n° source of the pixel SIT.

(5) At time t, the pulse φ3 becomes the old gh level, and the source line is connected to the load resistor RL through the switch MO3FET Ts (on-resistance R0,). Output ■. 0 changes over time and is given by the following equation.

FIG. 8 shows temporal changes in the gate potential VC% source potential v8 and output V out of the pixel SIT when the horizontal selection pulse φS is at the old gh level. In Figure 8,
When the horizontal selection pulse φ3 reaches the old gh level, the pixel SIT
The p1 gate and the n''' source of are in the forward direction, and the ρn diode current flows, and the signal charge accumulated in the gate capacitance is
Spills into the source.

Therefore, in this solid-state imaging device, the optical signal charge is destroyed, and both the gate potential VG and the source potential V decrease to 1.
Output ■ given by equation (6) above. , is smaller than the value obtained when the above equation (5) is substituted for Vt(t) in the same equation (6).

FIG. 9 shows the circuit configuration of another example of a solid-state imaging device already developed by the applicant. In this example, the switch MO3FET13-1.13- that constitutes the horizontal selection switch
2. ---. A MOS FET 18-1, 18-2. for column line potential amplification is connected to the drain of each of 13-4. -~1
8-4 are respectively connected, and each gate of these MO3FETs for column line potential amplification is connected to the corresponding column line 11.
-1.11-2. ---, 11-4, the drain is commonly connected to the board power supply VDD, and the video line 14
MO for video line reset is connected in parallel with load resistor RL.
A 3FET 19 is connected, and the other circuit configuration is the same as that shown in FIG. 4B.

In this solid-state imaging device, the reset MO3FET
By applying the video line reset pulse φIIV as shown in FIG. 10 to the gate of 19 and applying the drive pulse shown in FIG. 5 to the corresponding element, it operates in the same manner as the solid-state imaging device shown in FIG. 4B. In addition, you can
Without destroying the optical signal charge accumulated in the gate capacitance of the pixel SIT (an output corresponding to the optical signal charge can be taken out in the next readout period).

Here, the output voltage ■ when this solid-state imaging device is operated with the drive pulse shown in FIG. ut is Vout = a (Vs(tn) −V?+ −−
--(represented by 71. In addition, ■a is the dark value voltage of MO3FET18 for column line potential amplification, and a is the voltage gain of the source follower composed of MO5FET1B for column line potential amplification, switch MO3FET13, and load resistor RL. By substituting the above-mentioned equation (5) into this equation (7), -V, -Va) ----(8) is obtained.

As is clear from the above equation (7), in this solid-state imaging device, no output appears unless the source potential V becomes equal to or higher than VT. Therefore, in this solid-state imaging device, when the selected pixel is dark (Qoh"O), .

V, so that ≧0. +VIIl value is set.

[Problem that the invention seeks to solve]

The solid-state imaging device using SIT described above can effectively solve the above-mentioned drawbacks of those using MOS transistors, CCD5BBDs, etc., but according to various experiments conducted by the present inventors, it has low blooming resistance. There's a problem. This pluming will be explained below.

First, in the solid-state image pickup device shown in FIG. - source current) flows, and the potential of the column line to which this pixel SIT is connected rises. At this time, when another pixel SIT on the same column line is selected,
The above-mentioned non-selected pixel S along with the original output of that pixel SIT
The output of IT appears at the load resistor RL terminal. As a result, TV
Blooming is observed as white vertical stripes on a monitor.

Here, the gate potential of the unselected pixel SIT is set to ■.

Consider the amount of light required to raise the temperature to .

Now, in FIG. 4B, it is assumed that only the pixel S I Tl0-33 is irradiated with light and the other pixels SIT are not irradiated with light, and when the pixel S I Tl0-23 is selected, the output Try to find the amount of light that appears. FIG. 11 shows this situation. Here, for the sake of simplicity, a case of non-interlaced scanning will be shown. The output saturation is achieved by applying a reset pulse φ during the horizontal blanking time tllL.
R is applied and the gate potential V is clamped to φ, so that the rate of change of the gate potential V6 corresponding to the saturated light amount is 1"imL (shown by the imaginary line in Fig. 11). is expressed as where Tr is the field time.

On the other hand, when the pixel S I Tl0-23 is selected, the gate potential of the pixel S I T10-33 is VGIO-:13 with respect to the amount of light in which the output of the pixel S I Tl0-33 appears.
The rate of change m' (the slope of the straight line shown by the solid line in FIG. 11) is the pixel S I Tl0-33 is the third in the column direction, and a false signal appears at the pixel read timing of the line before the original pixel read timing. Then, it becomes . Here, t5 indicates the period of the horizontal scanning pulse in the horizontal scanning circuit 15.

As is clear from FIG. 11 and equations (7) and (8), +111st >m'. This means that the amount of light at which a false signal begins to appear when the pixel S E Tl0-23 is selected is smaller than the saturation amount of light. In reality, the amount of light observed as white vertical stripes on a TV monitor requires a light amount several times the saturated light amount, but in any case, the resistance to pluming is extremely low.

Next, the occurrence of pluming in the solid-state imaging device shown in FIG. 9 will be explained. In FIG. 12, as in the above case, only the pixels S I Tl0-33 are irradiated with light,
When pixel S I T10-23 is selected, image S I
This shows how the outputs of T10-33 appear.

In this case, the gate potential VGI corresponds to the amount of light at which the false signal of the pixel S I T10-33 appears. The rate of change # of -3 (the slope of the straight line shown by the solid line in FIG. 12) is the same as in the above case.

That is, in this solid-state imaging device, the saturation light amount m
It is resistant to blooming up to a light intensity of /1lltat times. Compared to the case of FIG. 4B, this is because the gate potential VGI
. This is because an extra amount of light is required to increase -3, by v7. This plumping resistance Im'/Tll*
According to the device prototyped by the applicant, at is ■
7・0.8(V), V, = 0.3(V), φ8・0
．． 8(V), CG/CG+CJ □ 0.6, V R
3 = 3 (V) Te, this value is the amount of light required for a false signal to appear at the right edge of the TV monitor, and in reality it requires an even greater amount of light to be observed as a white vertical stripe. , this is still not enough.

The present invention was made in view of these problems, and it is an object of the present invention to provide a solid-state imaging device suitably configured to have extremely high pluming resistance.

[Means and operations for solving the problem] In order to achieve the above object, the present invention is arranged in a matrix between a plurality of row lines and a plurality of column lines, with gate electrodes in the row lines and one main electrode. The signals accumulated in a plurality of images SIT each connected to a column line are read out all at once for each row line during a predetermined readout period by a driving means, and the signals accumulated in a plurality of images SIT are connected to each column line through a sample transistor. The potential is held at the gate of the potential amplifying transistor and sequentially read out within the horizontal scanning period, and in order to prevent the occurrence of pluming due to superimposition of signals from non-selected pixels SIT, a clamping means is used to hold the voltage at the gate of the potential amplifying transistor, and read out the potential amplifying transistors sequentially within the horizontal scanning period. During the period, the gate potential of all pixels SIT exceeding a predetermined potential at which no pluming occurs is clamped to the predetermined potential.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In this embodiment, for convenience of explanation, an array of 4 rows and 4 columns is shown, and elements having the same functions as the circuit configurations shown in FIG. 4B and FIG. 9 are given the same reference numerals. This is an indication. Static induction transistor (SIT) 10 forming each pixel and having the same structure as that in FIG. 5A
-11.10-12. --10-14.10-21.1
0-22. ---10-24. ---10-44 are arranged vertically and horizontally in a matrix, and each source of the SIT arranged vertically is connected to a column line 11-1.11-2. ---The gates of the SITs commonly connected to the row lines 12-1, 12-2, . ---12-
4 respectively. Column line 11-1.11-2.
---11-4 is sample MOS FET2O
-L 20-2. ---20-4 drain-source path as a drive transistor for column line potential amplification MO3FE718-1□18-2. ---18-
Connect to each gate of 4, sample MOS F
ET20-1.20-2. ------- Sampling and holding pulses φ and H are commonly applied to each gate of 20-4. In addition, MOS FET for column line potential amplification
18-1.18-2. ---, the drains of 1B-4 are commonly connected to the substrate power supply ■DD, and their sources are the switches MO3FET13-1.
13-2. --- Connect to video line 14 via 13-4. Switch M OS F E T13-1.1
3-2゜----13-4 each gate is horizontal scanning circuit 1
5 to apply a horizontal scanning pulse φ1. φSt+---φ3
Apply 4.

Also, a load resistor RL and a reset MO3'FET 19 are connected in parallel to the video line 14, and a reset MO3'FET 19 is connected in parallel to the video line 14.
A video line reset pulse φ is applied to the gate of the O3FET 19. On the other hand, perform in 12-1°12-2.
---12-4 is connected to the vertical scanning circuit 16 to apply a vertical scanning pulse φ(1+φGl+----φ, , 4. Furthermore, the column line 11-1.11-2.----11- 4
MOSFE T2O-1,20 for the sample of
-2, ---The end opposite to the side connected to 20-4 is a reset MO3F E721-L 21-
2. ---21-4 to ground, and a reset pulse φ of the pixel SIT is commonly applied to each gate of these reset MOSFETs.

In this embodiment, these reset MO3FET21
-1.21-2. --- In addition to resetting the pixel SIT described above, 21-4 is used to reset the gate potential of the pixel SIT as described above for the pixel SIT whose gate potential exceeds a predetermined potential at which blooming occurs when the pixel SIT is not selected, as will be described later. An action of clamping to a predetermined potential is performed. Note that S I Tl0-11°10-12. which constitutes the pixel. ---
-10-44 each drain is a drain power supply■. Commonly connected to.

The operation of the solid-state imaging device shown in FIG. 1 will be described below with reference to the drive pulse timing chart shown in FIG. 2. Vertical scanning pulse φGi=VR3(i・1.2.--
-4) When the pixel reset pulse φe turns on,
The gate potential of pixel SIT is φ8, the source potential is GND
will be reset to Further, when φGi+φS is turned off, the gate of the pixel SIT becomes a reverse bias state and starts light integration.

After a predetermined integration time, φ(ii” VIID),
The gate of pixel SIT in the i-th row line is biased to the read state. In this state, sample MO3F E
When the sample hold pulse φ□ applied to the gates of T2O-1, 20-2, ---20-4 is set to the old gh level, the source potentials of the pixels SIT on the i-th row line are all changed to the sampling MOS F. E T2O-1゜20-2. ---20-4 to the gates of column line potential amplification MO3FET1B-1, 18-2, ---18-4, and even after φSH is set to Low level, the column line potential amplification MO3FET1B remains unchanged. Retained by gate capacitance.

After that, φG8 is set to Low level. In addition, φ6. =
■. The timing may be after φ is set to the old gh level. Also, φ is turned on after φ■ is turned off, and the vertical scanning pulse φ of the next line is generated. ,. , is Vl
Turn off immediately before lfl, and φ. +(
i・1.2. ---4) is set to V□ at the same timing as φsu or during the period when φe is at the old gh level. The voltage signal V Zij held in the gate capacitance of MO3FET1B for column line potential amplification is a horizontal scanning pulse φ1j (j・1゜2, ---4) during the period when φ3□ is at LoV4 level.
) is read out sequentially by turning on the switch MO3FET13. Here, the output voltage V. U, is the voltage gain of the source follower composed of the column line potential amplification MO3FET 18, the switch MO3FET 13, and the load resistor RL, and then V out=a V' sij
--------(2).

As is clear from the above description, in this embodiment, VR5 and ■ to the gate of pixel SIT. The application timing is opposite to that in FIGS. 4B and 9 described above. That is, in this embodiment, φ,=V11. and φN
``The period when the old gh level is the horizontal scanning period tH
or the last fixed period of LH, and φ
. =■. The period during which φ, N=High level is within the horizontal blanking period.

Next, blooming in this embodiment will be explained. As in the case described above, the non-selected pixel S I Tl0
Assume that only -33 is irradiated with light. Gate potential VGI in pixel S I Tl0-33 in this case
. -33, source potential VSI. -13 is shown in Figure 2. As is clear from FIG. 2, the non-selected pixel S I
Even if Tl0-33 is irradiated with strong light that exceeds the saturation light amount,
φG ” VR3% φ8 During the period of the old gh level, the gate potential V GI.-33 is clamped to φ.

Gate potential VG of this unselected pixel S I Tl0-33
I. The reason why −3° increases due to light irradiation is that the gate
The source is in a floating state only during the period when φ is at a low level, and the source potential Vt111-1
It is only until the sample hold is completed that a continuous signal can be generated even if the signal rises by 2. Furthermore, in this embodiment, as in the case of FIG. 9 described above, the source potential V! 10-:1
1 does not exceed 71 of MO3FE718 for column line potential amplification, that is, the gate potential V G IVGIO-3
No output appears unless 3 becomes (vp+vy) or more.

From the above, in this embodiment, the gate potential VGI corresponds to the amount of light at which blooming begins to occur. -1, rate of change m″″ (slope of the straight line shown by the solid line in Figure 2)
is the period when φ is at the old gh level, and tH1φ8 is Lo-
If t BL/n is the time from when φ and H become low level, it becomes lL. On the other hand, the gate potential VG for the saturated light amount
The rate of change m, □ of IO-3ff (the slope of the straight line indicated by the imaginary line in FIG. 2) is given by the above equation (9).

Therefore, the amount of light at which blooming starts to occur is m''/m,... times the saturation amount of light, and as in the case of Fig. 9, v, = 0.8 (v), ■, 0.3 (V). ,φ,
=0.8(V), CG/(CG-CJ) □ 0
．． When calculated as 6, Vis 3 (V), it becomes.

The above value is the amount of light necessary for a false signal to appear at the right end of the TV monitor, and an even greater amount of light is required for it to actually be observed as white vertical stripes. In any case,
According to this embodiment, the blooming resistance is about 400 times higher than that of the one shown in FIG. 4B, and about five times more than that of FIG. 9, and therefore high image quality can be obtained. Furthermore, since there is no difference in integration time due to difference in horizontal scanning time, the integration time is the same for all pixels, and since the integration time is also the same for pixels that share a common row line, it has the function of a focal plane shutter. That is, the timing at which the vertical scanning pulse φ6 is set to the reset voltage Vl11 is 1.
It is possible to set the photocharge integration time to any horizontal scanning period within the field time T, thereby changing the photocharge integration time from the horizontal blanking time tlL to the one field time T, time (
Since it can be arbitrarily set in units of tII+tsL), it has a shutter function. Further, when the reset pulse φ6 is at the old gh level, the vertical scanning pulse φ.

By setting 0(v), non-destructive readout becomes possible, and new applications in fields such as image processing and measurement can be expected.

3A to 3C show essential parts of a modification of the present invention, in which elements having the same functions as in FIG. 1 are given the same reference numerals.

FIG. 3A shows the column line potential amplification MO3FET18-1.
18-2. ---1 is connected to the outputs φSI+φ, 2-1- of the horizontal scanning circuit instead of the substrate power source VDD.
wiring becomes unnecessary.

FIG. 3B shows the column line potential amplification MO3FET18-1.
18-2. ---It turns on/off the connection of the power supply vno to the drain of the column line potential amplifying M
OS F E T18-1.18-2. --- one source is commonly connected to the video line 14, and these M sources are
OS FET drain and horizontal selection switch MOS F
ET13-1.13-2. At the connection points with -m-, there is a MOS F E in order to reset these connection points.
T22-1.22-2. --- Connect one. M.O.
S F E T22-L 22-2. -1 gate has a horizontal selection pulse φ, 1. Reset MO3 for resetting the video lines 14 to turn them on during the period when φSZ+ is in a low level state.
The same pulse φi as the reset pulse φRV applied to the gate of the FET 19 is supplied.

Figure 3C shows the sample MOSFET2O-1,
20-2゜---One source and column line potential amplification MO
S F ET18-1.18-2. --- Connection with the gate of horizontal selection switch MOSFET T13-L
13-2. --- is turned on and off by MO3FET1B-1, 18-2, -m for column line potential amplification.
- drain and switch MO3FET13-1.13-
2. -m- gate and the output φ of the horizontal scanning circuit, 1. φ
Connect to S2+--- and switch MO3F ET13-
1.13-2. -1- source and column line potential amplification M
OS F ET18-1.18-2. At the connection points with -m-, there is an M OS to reset these connection points.
FET22-1.22-2. --- Connect.

These MOSFE T22-1.22-2. −
--The horizontal selection pulses φ3I, φ3! are applied to the first gate as in the case of FIG. 3B. .

---During the period when one is in a low level state, these MO
S F E T22-1.22-2. -m- is supplied with a pulse force to turn it on.

The same effects as those shown in FIG. 1 can also be obtained with these modified examples.

〔Effect of the invention〕

As described above, according to the present invention, the signals accumulated in the pixels SIT arranged in a matrix are read out and held for each row line all at once during a predetermined readout period,
They are sequentially read out within the horizontal scanning period, and the gate potential of all pixels SIT exceeds a predetermined potential at which blooming does not occur during a period other than the predetermined readout period. Since the voltage is clamped to the predetermined potential, blooming resistance can be improved and high image quality can always be obtained. Furthermore, since pixel signals are held and read out for each row line, a large output voltage can be obtained. Furthermore, since the integration times for all pixels are equal and the integration times are equal for each row, there is an effect of having a focal brain shutter function.

Furthermore, by partially changing the drive pulse timing, non-destructive continuous operation can be achieved, which makes it possible to achieve
, new applications are expected in fields such as image processing and measurement, which were not possible with CCD image sensors.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram showing an embodiment of the present invention, Fig. 2 is a signal waveform diagram for explaining its operation, and Figs. 3A and B.
4A and 4B are diagrams showing the main parts of a modification of the present invention, respectively; FIGS. 4A and 4B are a structural diagram of one pixel and an overall circuit configuration diagram of an example of a solid-state imaging device already developed by the applicant; Figure 5 is a signal waveform diagram for explaining its operation, Figure 6 is a circuit configuration diagram focusing on one pixel of a conventional solid-state imaging device, and Figures 7 and 8 are diagrams for explaining its operation. 9 is a circuit configuration diagram of another example of a solid-state imaging device already developed by the applicant; FIG. 10 is a signal waveform diagram of the main part to explain its operation; FIG. A waveform diagram for explaining the occurrence of bloom mink in the solid-state imaging device shown in B, and FIG.
FIG. 3 is a waveform diagram for explaining the occurrence of blooming in the solid-state imaging device shown in the figure. 1... Silicon IJ substrate 2... Epitaxial layer 3... Source region 4... Gate region 5.
...Capacitor 6...Isolation region 10-11.
10-12. ---10-44...5IT (pixel) 1
1-1.11-2.11-3.11-4... Column line 12-1.12-2.12-3.12-4... Row line 13-1.13-2.13- 3.13-4...Horizontal selection switch 03FET 14...Video line 15...Horizontal scanning circuit 16...Vertical scanning circuit 18-1.18-2.18-3゜18-4... MOSFET19 for column line potential amplification
・MO3FET20-1.2 for video line reset
0-2.20-3.20-4...MO3F for sample
ET21-1. ．． 21-2.21-3.21-4...
MO5FET22-1.22-2...MO for reset
S F ET Figure 2 Vaat Figure 3 Figure 3 C Figure 5 φF Figure 6 Figure 9 Figure 1I ``; Commissioner Kuro 1) Akio Yu 1, Indication of the case Patent Application No. 277346 of 1985 2, Name of the invention Solid-state imaging device 3, Person making the amendment Relationship to the case Patent applicant (037) Olympus Optical Industry Co., Ltd. 4. Agent 1. Correct formula (3) on page 8 of the specification as follows. c 2. "For column line potential amplification" on page 11, lines 3-4.
"For drive use" should be corrected, "For column line potential amplification" in lines 5 and 6 of the same page should be corrected to "for drive use", and "Substrate" should be deleted in line 8 of the same page. 3. Correct "for column line potential amplification" to "for drive" in lines 5 and 6 to 7 of page 12. 4. R(7), +8) formula in the 12th line from the bottom of No. 15.
Correct it to "r (9), αω formula" and correct "to be observed" in the 8th line from the bottom to "to be observed". 5. Correct "pixel 5ITJ" in lines 11-12 of page 17 to "pixel 5ITJ", and correct "column line potential amplification transistor" in row 15 of the same page to "MO3FETJ for drive". Delete "For column line potential amplification as a transistor" on page 18, lines 19 and 20. 7. Correct "For column line potential amplification" to "For drive" in the 4th line of page 19, and delete "Substrate" in the 6th line of the same page. 8. Correct "for column line potential amplification" to "for drive" in lines 8, 10-11, and 19 of page 21 of the same page. 9. Correct "for column line potential amplification" to "for drive" in the fourth line of page 22. 10. In the 14th line of page 23, "for column line potential amplification" is corrected to "for drive". 11. Correct "φ," in line 15 of page 25 to "φR". 12. Corrected "For column line potential amplification" in the 2nd, 7th, and 9th rows of the same page to "Drive", and changed "Substrate" in the 3rd and 5th rows of the same page, respectively. delete. 13. "For column line potential amplification" in the 3rd, 6th, and 10th to 11th lines of page 27 is corrected to "drive". 14, page 28, lines 12-13, “Because it is read out,”
Correct it to "Because it is read out." 15. "Blooming" on page 29, line 20 is corrected to "blooming." 16. Correct the rlB-4- column line potential amplification MO5FETJ in the 14th row of page 30 to rlB-, t-...drive MO5FETJ.

Claims (1)

[Claims] 1. A plurality of electrostatic conductive transistors arranged in a matrix between a plurality of row lines and a plurality of column lines, each having a gate electrode connected to a row line and one main electrode connected to a column line. , a drive transistor connected to each of the plurality of column lines via a sample transistor, and signals accumulated in the electrostatic induction transistors are read out simultaneously for each row line during a predetermined readout period to obtain the sample. drive means for holding the signal in the drive transistor via the drive transistor and sequentially reading out the held signal within a horizontal scanning period; 1. A solid-state imaging device, comprising: clamping means capable of clamping the voltage to a predetermined potential such that blooming does not occur. 2. The solid-state imaging device according to claim 1, wherein the predetermined readout period is shorter than a clamping period by the clamping means. 3. The predetermined reading period and the time at which the drive transistor holds the signal read during that period are set within the horizontal blanking period, and the clamping period by the clamping means is set within the horizontal scanning period. A solid-state imaging device according to claim 1 or 2, characterized in that: