JPS63131567A - Storage device - Google Patents

Abstract

PURPOSE:To improve the degree of integration, and to reduce power consumption by burying a gate electrode for a MOS transistor into a trench so that the direction tying the opening section and bottom of the trench formed to a semiconductor base body is directed in the direction of gate length and shaping a resistance element onto a semiconductor substrate. CONSTITUTION:Gate electrodes 17a, 17b for MOS transistors 3, 4 constituting an inverter for a flip-flop are buried into trenches 15a, 15b shaped to semiconductor base bodies 11, 13 so that the direction tying the opening sections and bottoms of the trenches 15a, 15b is directed in the direction of gate length. Consequently, the area of a memory cell is made smaller than the gate electrodes 17a, 17b are formed onto the semiconductor base bodies 11, 13. Resistance elements 5, 6 are shaped onto the semiconductor substrate 11 and the epitaxial layer 13, and one power line 28 of two power lines 28, 29 is also used for an adjacent memory cell. As a result, either of the resistance elements 5, 6 can be lengthened, thus ensuring a high resistance value. Accordingly, the degree of integration is improved, and power consumption can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention uses a memory cell configured using a flip-flop, and an inverter consisting of a MOS transistor and a resistance element connected to the Mo3 transistor. The present invention relates to a memory device in which the flip-flop is configured.

[Summary of the invention]

The present invention provides a memory device as described above, in which the gate electrode of the MOS transistor is buried in the semiconductor substrate so that the width direction of the gate electrode is perpendicular to the surface of the semiconductor substrate,
By forming the resistance element on a semiconductor substrate, it is possible to achieve a high degree of integration and reduce power consumption.

[Conventional technology]

As for memory devices, higher integration is always being pursued. For this purpose, the present applicant has developed a semiconductor substrate in which the gate electrode of the Mo3 transistor constituting the flip-flop and the resistance element are arranged so that the width direction of the gate electrode and the longitudinal direction of the resistance element are perpendicular to the surface of the semiconductor substrate. He previously proposed a memory device embedded in the body to increase the degree of integration in Japanese Patent Application No. 61-231699.

[Problem that the invention seeks to solve]

However, if the depth of burial is too deep, the burial itself becomes difficult, so there is a limit to the depth of burial.

For this reason, the resistance element cannot be made very long,
There is a problem that the resistance value becomes low and the power consumption increases.

Even if the resistance element is short, if its specific resistance is high, the resistance value will be high and power consumption can be reduced. For this purpose, 5IPOS (Semi
-Insulating POlycrystall
It is also possible to use ``ine 5 ilicon'' etc.

However, this time, since the etching rates of 5IPO5 and SiO2 are close, 5lot cannot be used as an etching stopper for 5IPOS, resulting in a problem that processing becomes difficult.

[Means for solving problems]

The memory device according to the present invention includes 3.4 MOS transistors.
The width direction of the gate electrodes 17a and 17b is the semiconductor substrate 11.
．． The gate electrode 17a is perpendicular to the surface of the gate electrode 13,
17b is embedded in the semiconductor body 11.13, and a resistive element 5.6 is formed on the semiconductor body 11,13.

[Effect]

In the memory device according to the present invention, the width direction of the gate electrodes 17a and 17b of the MOS transistor 3.4 constituting the inverter of the flip-flop is aligned with the semiconductor substrate 11.13.
The gate electrodes 17a, 17b are arranged perpendicular to the surface of the gate electrodes 17a, 17b.
Since the gate electrode 17a117b is buried in the semiconductor body 11.13, the area of the memory cell is smaller than that in the case where the gate electrode 17a117b is formed on the semiconductor body 11.13.

Furthermore, since the resistive element 5.6 constituting the inverter of the flip-flop is formed on the semiconductor substrate 11.13, if this resistive element 5.6 is formed on other elements, the memory cell This resistance element 5.6 can be made longer to increase its resistance value without increasing its area.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 to 3.

FIG. 1 and FIG. 2 show this embodiment.

As shown in FIG. 2, one memory cell of this embodiment has a switching transistor 1.2, a driver transistor 3.4, and a resistance element 5.6.

In order to manufacture this embodiment, as shown in FIG. 1, a ground electrode 12 is first formed by N2 diffusion on a predetermined portion of the surface of a P-type semiconductor substrate 11.

Next, a P-type epitaxial layer 13 is grown on the surface of the semiconductor substrate 11, and an element isolation region 14 is formed on the surface of this epitaxial layer 13. Then, grooves 15a and 15b reaching at least the ground electrode 12 are formed in the epitaxial layer 13 and the semiconductor substrate 11, two for each memory cell, as shown in FIG. 3A.

Next, gate insulating films 16a and 16b of the driver transistor 3.4 are formed on the inner wall surfaces of the grooves 15a and 15b, and then the grooves 15a and 15b are filled with polycrystalline Si, and these polycrystalline Si are used to form the driver transistor 3.4. 4 gate electrode 17
a, 17b are formed.

These polycrystalline Si are doped with phosphorus.

Next, a gate insulating film 18 is formed on the surface of the epitaxial layer 13.
As shown in FIG. 3A, openings 21a, 21b and 21C, 21d are formed in portions of the gate insulating film 18 corresponding to the electrical connections with the trenches 15a, 15b and the epitaxial layer 1f13.

Next, by depositing and patterning a first layer of polycrystalline Si, as shown in FIGS. 1 and 3B,
Conductive wire 22 connecting opening 21a and opening 21d, opening 2
A conductive wire 23 and a word line 24 are formed to connect 1b and the opening 21C.

Then, by doping N2 impurities using the conductive wires 22, 23, word line 24, etc. as masks, the switching transistor 1 is doped as shown in FIGS. 1 and 3B.
and the source/drain region 2 of the driver transistor 3
5a, 25b and source/drain regions 25c, 25 of the switching transistor 2 and driver transistor 4
d. Note that in order to form a source/drain region 25b also under the conducting wire 23, this portion is doped with N impurity in advance before depositing the first layer of polycrystalline St.

Next, as shown in Fig. 1 and Fig. 3C, the Sin
forming a glabellar insulating film 26 by depositing ,
Furthermore, openings 27a and 27b are formed in the glabellar insulating film 26 at portions corresponding to the grooves 15a and 15b.

Next, by depositing and patterning a second layer of polycrystalline Si, as shown in FIGS. 1 and 3D,
Power supply lines 28 and 29 and resistance elements 5 and 6 are formed. Note that by doping impurities into the portions of the 2N-th polycrystalline Si that will become the power supply lines 28 and 29 and the portions near the openings 27a and 27b, the resistance value of these portions is reduced.

Thereafter, the glabellar insulating film 31 is formed by depositing SiO□ by CVD, and the openings 32a and 32b penetrating the glabellar insulating film 31.26 and the gate insulating film 18 are formed in the source/drain regions 25a and 25a of the driver transistor 1.2. 2
5C, and data lines 33 and 34 are formed at AJ.

In this embodiment, the gate electrodes 17a, 1 of the driver transistor 3.4 constituting the flip-flop are
The width direction of 7b is the semiconductor substrate 11 and the epitaxial layer 1
It is perpendicular to the surface of 3. Moreover, the resistance element 5.6 is
It is formed on a semiconductor substrate 11 and an epitaxial layer 13.

Further, in this embodiment, two power supply lines 28 and 29 are used, but as is clear from FIG. 3D, one of the power supply lines 28 and 29
8 is also used in an adjacent memory cell. For this reason, only 1.5 power supply lines are substantially used for one memory cell.

Since the power supply lines 28 and 29 are used in this manner, the lengths of the resistance elements 5.6 are equal, and the resistance values of these resistance elements 5.6 are balanced. Also, both of the resistor elements 5 and 6 can be made longer, so that the power supply! 2B, 2
The influence of diffusion of impurities from 9 etc. can be reduced, and a high resistance value can be ensured.

Furthermore, in the earlier Japanese Patent Application No. 61-231699, both the gate electrode and the resistance element are formed in the groove, but in this embodiment, the gate electrodes 17a and 1 are formed in the grooves 15a and 15b.
Only 7b is formed.

For this reason, in this embodiment, processing stability is high and yield can be easily improved.

In this example, the N-diffused ground electrode 12 was formed on the surface of the P-type semiconductor substrate 11, and the P-type epitaxial layer 13 was grown on the semiconductor substrate 11. After growing the P-type epitaxial layer of the first layer and forming the N′ diffused ground electrode on this epitaxial layer, a second P-type epitaxial layer may be further grown.

Further, in this embodiment, the conductor wires 22, 23 and the word line 24 are formed of the first layer of polycrystalline St, and the power supply wires 28, 2
9 and the resistive element 5.6 are formed of the second layer of polycrystalline Si, but only the conductor 22 and the word line 24 are formed of the first layer of polycrystalline Si, and the conductor 23 is formed of the second layer of polycrystalline Si. The power supply line 29 and the resistive element 5.6 may be formed of a third layer of polycrystalline Si.

In this way, there is no need to pre-dope the source/drain regions 25b of the switching transistor and driver transistor 3 with N+ impurities prior to depositing the first layer of polycrystalline St.

〔Effect of the invention〕

In the memory device according to the present invention, the area of the memory cell is small and the resistance value of the resistance element can be increased, so that the degree of integration is high and the power consumption can be reduced.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and FIG. 3 shows an embodiment of the present invention. -1
2 is a circuit diagram of a memory cell to which the present invention can be applied, and FIG. 3 is a plan view sequentially showing the manufacturing process of an embodiment. In addition, in the symbols used in the drawings, 3.4-・-・-・・−・・−・−・Driver transistor 5.6・・−・・−・−・・−・Resistor fi element 11
・・−−−−〜−−・−・・−・・Semiconductor substrate 13−・
-・-・--------Epitaxial layer 17a,
17b =----gate electrode.

Claims (1)

[Claims] A memory device in which a memory cell is configured using a flip-flop, and the flip-flop is configured using an inverter consisting of a MOS transistor and a resistance element connected to the MOS transistor. , a memory device in which the gate electrode of the MOS transistor is embedded in the semiconductor substrate so that the width direction of the gate electrode is perpendicular to the surface of the semiconductor substrate, and the resistor element is formed on the semiconductor substrate. .