JPS631294A - Time switch - Google Patents

Abstract

PURPOSE:To increase the number of handlable lines up to the full channel capacity of a time switch by providing a channel memory with a function circuit which issues a tone signal, a PB signal, or the like and providing a read address control memory with a discrimination code address and switching a switch in accordance with contents of a discrimination code in this address. CONSTITUTION:In case plural function circuits are provided, function circuits are alternatively switched by a switch 9. For example, when the function circuit for the tone signal is used, various tone colors are prepared, and an address is assigned to each of these outputs. These addresses are accessed by an address output 5b of a read address control memory 5 to output PCM data of the tone signal of respective tone colors. Consequently, a specific tone signal is supplied to a specific time slot on output highways 7a, 7b, ... through the switch 9 and a distributor 6 when the discrimination code outputted from the control memory 5 is 0 and remainder address data designates the address of this specific tone signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a time switch for exchanging cooperative input/output data in a digital exchange.

BACKGROUND OF THE INVENTION FIG. 3 shows a time switch of a conventional digital exchange, and 31 is a switch circuit having a switching function. - In general, switch circuits include a communication path memory, a concentrator that collects a large number of large highways and supplies them to the communication path memory, a distributor that distributes data read from the communication path memory to a plurality of output highways, and a communication path memory. The switch circuit 31 shown in the figure is composed of a write address counter that specifies reading of data to the channel memory, and a read address control memory that specifies reading of data to the channel memory. There is.

In this switch circuit 31, call data is written from the left side and taken out from the right side.

During the period from when the data is written to the switch circuit 31 until it is read, the write time slot and the read time slot are exchanged, and communication paths are exchanged. In the illustrated example, input data on the line 34 is written from point A and output to point D by switching action. This output data is led to, for example, a conference trunk 32 as a miscellaneous trunk, undergoes conference trunk processing, and then returns to the switch circuit 31 from point B.
added to. The signal is then output to point F by the switching action of the switch circuit 31 and supplied to the line 35. 33 is a miscellaneous trunk, for example, a talkie trunk, and the audio data output from this trunk is sent from point 0 to the switch circuit 3.
1, outputted to point E by exchange action, and connected to line 3.
6.

By the way, in the conventional means described above, points A, E, and F are input/output points selected by another control device, and they vary to other positions during actual operation. Point B, point 0, and point D are the input/output points of the conference trunk 32 and talkie trunk 33, so they are determined from the beginning and do not change.This means that these communication paths are fixed, so As a result, there is a problem in that the number of lines that can be handled by a digital exchanger cannot be increased to the communication path capacity of a time switch.In recent years, digital exchanges have introduced various convenient functions. The problem described above is becoming more serious as the rate at which communication paths are occupied is increasing as the number of communication channels increases and data devices are combined.

The technology disclosed in JP-A-60-25398 and JP-A-60-14591 is a technique for constructing a birdware at low cost by improving the time switch, and as a result increases the number of lines. It is not a means to increase the number of lines, and it does not provide a satisfactory solution to the problem.

In view of these points, it is an object of the present invention to provide an extremely useful time switch that can allocate the entire communication path capacity as the number of lines that can be handled.

In order to achieve the above object, the present invention writes data on a large highway obtained by time-division multiplexing the digital outputs of each copic into a communication channel memory according to the designation of a write address counter, and reads the data. A time switch that reads data written in the communication path memory according to the designation of the address control memory and supplies it to the output highway is provided with a functional circuit that emits a tone signal and a PB double signal in parallel with the communication path memory. , the communication path memory and the functional circuit are selectively connected to the output highway by a switch provided on the output side of the communication path memory, and a discrimination code address is provided in the read address control memory, and this address The switching device is characterized in that the switching device is switched depending on the content of the discrimination code within.

The operation of the present invention will be explained in detail in the following examples.

Figure 1 shows a digital interface as an embodiment of the present invention.
■ indicates the time switch of the large highway 2a12b, which consists of the digital output of each copier (not shown).
The above data is supplied to the communication path memory 3, which converts serially input audio data into parallel data and multiplexes it.

The communication path memory 3 is used to write and read voice data and exchange communication paths during this time.Writing is performed to an address specified by the output of the write address counter 4, and reading is performed to the address specified by the output of the write address counter 4. Perform this on the address specified by the output of .

The distributor 6 reversely converts the parallel signal read from the communication path memory 3 into a serial signal, and distributes and outputs the signal to a plurality of output highways 7a, 7b, . . . . The write address counter 4 is driven by clock pulses generated by the clock generator 8 and produces an output specifying the write address of the channel memory 3. This output is also applied to the read address control memory 5 and specifies the address of the memory 5.

The read control memory 5 only has the function of issuing an output specifying the read address of the communication path memory 3.
In the case of boat fishing, in the present invention, the memory area of the memory 5 is provided with a discrimination code address 5b in addition to the address 5a storing the contents specifying the read address of the communication path memory 3, as shown in FIG. The switch 9 is switched according to the discrimination code stored in this address.

In the embodiment, the switch 9 is switched so that when the discrimination code is "1", the output of the communication path memory 3 is enabled, and when the discrimination code is "0", the output of the functional circuit 1o is enabled. Note that the address contents of the read address control memory 5 are written through the signal distributor 11 by a control processor (not shown).

As the switch 9, for example, a multiplexer is used which performs a switching operation based on a discrimination code issued by the read address control memory 5.

The functional circuit 10 is a tone signal functional circuit with a function of generating a tone signal, a PB signal functional circuit with a function of generating a button signal, a three-way call function circuit, or a conference call function circuit. Various circuits are used.

Although the number of functional circuits used is one in the illustrated example, a plurality of functional circuits may be used. When a plurality of functional circuits 10 are provided, each functional circuit may be selectively switched using the switch 9. Here, a case will be described in which, for example, a tone signal functional circuit is used as the functional circuit 10.

In the case of tone signals, various tones such as busy tones, hold tones, ringback tones, and error tones are prepared, and addresses are assigned to their respective outputs. When these addresses are read and accessed by the address output 5b of the address control memory 5, the PCM data of the tone signal of each tone is output. This PCM data is updated every 125 μs, and the next time it is accessed, the next PCM data will be output. Therefore, when the discrimination code output from the read address control memory 5 is "0" and the remaining address data specifies the address of a specific tone signal, the tone signal is transmitted through the switch 9 and the distributor 6 to the output highway 7.
It will be supplied on specific time slots a, 7b, . . . Since this operation is repeated every 125 μs, a desired tone signal is sent on a specific time slot. According to the above configuration, when the discrimination code output from the read address control memory 5 is "1", the communication path memory 3 is enabled, the contents stored therein are read out, and the switching device 9 are supplied on predetermined time slots of the outbound highways 7a, 7b, . . . On the other hand, when the discrimination code output from the read address control memory 5 is "0", the functional circuit 10 is enabled, and the tone signal emitted from the functional circuit 1o is transmitted through the switch 9 to a predetermined time slot on the outgoing highway. Supplied on top.

As explained above, according to the present invention, by providing a discrimination code address in the memory area of the read address control memory and adding a switching device, the number of lines of the time switch can be changed internally to the exchange. There is no need to allocate tone signal circuits, talkie signal circuits, etc. used in the system, and the number of lines that can be handled can be increased to the maximum of the communication path capacity of the time switch.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a one-hour switch of the time switch of the present invention, FIG. 2 is a diagram schematically showing a part of the memory area of the read address control memory in FIG. 1, and FIG.
The figure shows a conventional time switch. 2a, 2b...Incoming highway, 3...Call path memory 4...Writing address counter, 5...Reading address control memory, 5b...Discrimination code address,
7a, 7b...Exit highway, 9...KiritQ B,
10...Functional circuit.

Claims (1)

[Claims] The data on the input highway obtained by time-division multiplexing the digital output of each codec is written to the communication path memory according to the designation of the write address counter, and written to the communication path memory according to the designation of the read address control memory. In the time switch that reads data and supplies it to the output highway, a functional circuit having a function of generating tone signals, PB signals, etc. in parallel with the communication path memory is provided, and is provided on the output side of the communication path memory. The switching device is configured to selectively connect the communication path memory and the functional circuit to the outgoing highway, and a read address control memory is provided with a discrimination code address, and the switching device is configured to selectively connect the communication path memory and the functional circuit to the output highway. A time switch characterized in that it performs switching.