JPS63127471A - Pcm signal regeneration circuit - Google Patents

Abstract

PURPOSE:To regenerate a PCM signal through the use of a simple circuit by D/A converting the PCM signal, sampling an output by the clock of a prescribed frequency, further, sampling it by the clock multiplied by an integer, and making it pass through an LPF. CONSTITUTION:The D/A converted output is amplified 12, 112, and if the clock of 44.1kHz is '1', 122 is grounded through a switch 22, and a signal is outputted. The switches 32, 132 are controlled by the clock of 44.1X2kHz, and from second sampling circuits 24, 124, the sampled signal of the double frequency of the output of the amplifiers 12, 112 is obtained. At that time, regarding a frequency spectrum, higher harmonic components other than a necessary frequency component come to only the spectrums centering at the integer-times of 44.1X2kHz, and the band spectrum of 44.1/2-44.1X3/2 is suppressed. Therefore, for rear stage LPFs 34 and 134, a low grade LPF with a loose attenuation characteristic can be used, then the PCM signal can be regenerated by the circuit constitution of a low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a PCM signal reproducing circuit, and more particularly to a PCM signal reproducing circuit for reproducing a PCM digital signal as an analog audio signal or video signal.

(Prior Art) Conventionally, this type of PCM signal regeneration circuit, for example,
CD (compact disc) device, DAT (digital audio tape) device, VTR with digital audio
(video tape recorder) or digital stereo broadcast receiving equipment. This kind of PCM
In the signal regeneration circuit, PCM (Pulse C
ode Modulation) digital signal to P
AM (Pulse Amplitude Mod
By converting the PAM signal into an analog signal (Lation), sampling the PAM signal, and passing it through a low-pass filter, a reproduced analog audio signal or analog video signal is obtained.

In a conventional PCM signal reproducing circuit, the output of the sampling circuit is directly applied to the low-pass filter, so that, in addition to the frequency components required as an audio signal, harmonic components of the sampling clock are also input to the low-pass filter. In order to remove such harmonic components, it is necessary to use a low-pass filter having steep attenuation characteristics. As such a low-pass filter, for example, a 7th to 11th order Chebyshev-type low-pass filter is used. This high-order low-pass filter not only has a complicated circuit configuration, but also has problems with the quality of the reproduced signal, such as deterioration of group delay characteristics in high frequencies.

Therefore, for example, in Japanese Patent Application Laid-Open No. 60-32167 published on February 19, 1985, a digital filter is installed as a recording side circuit, and the sampling frequency is doubled or quadrupled compared to the conventional one. It has been proposed to increase the number of filters to 1, thereby making it possible to use a low-order low-pass filter with a gentle attenuation characteristic.

(Problem to be Solved by the Invention) It is possible to make a playback circuit by making some changes to such a recording system, but in any case, when using a digital filter, a dedicated digital processing circuit is required. This not only complicates the circuit configuration but also increases the product cost.

Therefore, the main object of the present invention is to provide a PCM signal regeneration circuit that can use a low-order low-pass filter with a gentle attenuation characteristic with a simpler and cheaper circuit configuration.

(Means for Solving the Problems) Simply put, the present invention provides a DA converter for converting a PCM digital signal into a PAM analog signal;
a first sampling means for sampling the output of the A converter in response to a first clock having a predetermined frequency; and a second sampling means for sampling the output of the first sampling means in response to a first clock having a predetermined frequency; It is a PCM signal reproducing circuit comprising a second sampling means for sampling in response to a clock, and a low-pass filter receiving the output of the second sampling means. It is converted into an analog signal, ie, a PAM signal. A PAM signal obtained from this DA converter is sampled by a first sampling means in response to a first clock having a frequency of 44.1 kHz in the case of a CD device, for example. The output has a frequency that is an integral multiple, preferably an even multiple, of the first clock, for example 8 in the case of a CD device.
The sample is sampled by the second sampling means in response to the second clock signal at 8.2 kHz.

By sampling by this second sampling means, the frequency spectrum of the harmonic components input to the low-pass filter is shifted to a higher frequency range. For example, if a second clock with twice the frequency of the first clock is used, the only harmonic components other than the necessary signal components will be a spectrum centered at a frequency that is an integer multiple of the frequency of the second clock. The spectrum of harmonic components of the frequency of the first clock is suppressed.

(Effects of the Invention) According to the present invention, the harmonic components to the low-pass filter are shifted to a higher frequency range, so the low-pass filter is configured with a low-order filter such as a third-order Turworth low-pass filter. can do.

Furthermore, in order to make such a low-order low-pass filter usable, there is no need to use a complicated and expensive digital filter as in the past, and the overall circuit configuration is simple, so the product cost does not increase too much. .

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

(Embodiment) FIG. 1 is a circuit diagram showing an embodiment of the present invention. In this example and the following examples, the invention provides two
The description will be given assuming that it is used in a channel stereo type CD device. However, it should be pointed out in advance that the present invention is also applicable to other devices such as those mentioned above.

The PCM digital signal reproduced from the CD by optical pink-up (not shown) is transmitted to the left channel (L c
h) and right channel (Rch), and each is provided to a DA converter. Here, its left channel (
The Lch) signal path will be explained in detail, and the right channel (Rch) signal path will be given similar reference numerals.
Omit duplicate explanations.

From the buffer amplifier 12 included in the DA converter, the PC
A PAM signal is obtained by converting the M digital signals into analog signals. This PAM signal is given to the first sampling circuit 14.

The first sampling circuit 14 includes a buffer amplifier 16, and a feedback resistor 18 and a hold capacitor 20 are connected to the buffer amplifier 16. That is,
A hold capacitor 20 is connected between the (-) power and the output of the buffer amplifier 16, and the buffer amplifier 1
A feedback resistor 18 is connected between the output of the buffer amplifier 6 and the output of the buffer amplifier 12, that is, the input of the buffer amplifier 16. An analog switch 22 is connected between the output of the buffer amplifier 12 and the input of the buffer amplifier 16.

This analog switch 22 receives a first signal of a frequency of 44.1 kHz, for example, given from a clock source (not shown).
Operates in response to a clock. For example, when the first clock is at a low level, the output of the buffer amplifier 12 and the input of the buffer amplifier 16 are connected, and when the first clock is at a high level, the output of the buffer amplifier 12 is connected to ground.

In this way, the first sampling circuit 14 is configured.

The output of the first sampling circuit 14 is given to the second sampling circuit 24. This second sampling circuit 24 similarly includes a buffer amplifier 26, and a feedback resistor 28 and a hold capacitor 30 are connected in parallel between the input and output of this buffer amplifier 26. An analog switch 32 is connected between the output of the first sampling circuit 14 and the input of the buffer amplifier 26. This analog switch 32 operates in response to a second clock having a frequency of 88.2 kHz, for example, and when the second clock is at a low level, the output of the first sampling circuit 14 is transferred to the second sampling circuit 24, that is, the buffer. It is given as an input to the amplifier 26, and when it is at a high level, the output of the first sampling circuit 14 is connected to ground.

In this way, the second sampling circuit 24 samples the output of the first sampling circuit 14 in response to the second clock, and this output is provided to the low-pass filter 34.

The right channel PCM signal is processed in the same way as the left channel signal by components 112-132 that make up the lower path in FIG.
given to. However, analog switches 122 and 132 are reversed in their operation from corresponding left channel analog switches 22 and 32. That is, when the first clock is at a high level, the analog switch 122 supplies the output of the buffer amplifier 112 of the DA converter to the input of the buffer amplifier 116 that constitutes the first sampling circuit 114, and when the first clock is at a low level, it supplies the output of the buffer amplifier 112 of the DA converter to the input of the buffer amplifier 116 that constitutes the first sampling circuit 114. Connect the output of the terminal to ground. Similarly, the analog switch 132 provides the output of the first sampling circuit 114 as an input to the second sampling circuit 124, that is, the buffer amplifier 126 when the second clock is at a high level, and provides the output of the first sampling circuit 114 as an input to the second sampling circuit 124, that is, the buffer amplifier 126 when the second clock is at a low level. Connect the output of 114 to ground.

In operation, the buffer amplifiers 12 and 112 of the DA converter output analog signals, ie, PAM signals, as shown in FIGS. 2(A) and 2(B). Such a PAM signal is sampled by first sampling circuits 14 and 114 in response to a first clock. As shown in FIG. 2(C), the first clock repeats high level and low level at a constant frequency w1 (44, 1 kHz). When this first clock is at a low level, the analog switch 22 supplies the output of the buffer amplifier 12 to the first sampling circuit 14, and the analog switch 122 connects the output of the buffer amplifier 112 to ground. Therefore, at this time, the first sampling circuit 14 samples and holds the output of the buffer amplifier 12 at that time as it is. On the other hand, the first sampling circuit 114 of the right channel holds the previous sampling value.

Next, when the first clock turns to high level, the analog switches 22 and 122 operate in reverse, and the first sampling circuit 14 holds the previous sampling value, and the first sampling circuit 114 Then, the output of the buffer amplifier 112 at that time is held.

In this way, the first sampling circuits 14 and 1
14, sampling signals as shown in FIGS. 2(D) and 2(E) are obtained.

As shown in FIG. 2(F), a second clock signal having a frequency that is an integer multiple of the first clock, an even number multiple, for example twice, of the first clock is used.
A clock is given. The second sampling circuits 24 and 124 operate in the same manner as the first sampling circuits 14 and 114, and as a result, from these second sampling circuits 24 and 124, as shown in FIG.
A left channel signal and a right channel signal as shown in (H) are output. That is, the second sampling circuits 24 and 124 result in signals obtained by sampling the PAM signals obtained from the buffer amplifiers 12 and 112 of the DA converter at twice the sampling frequency.

The frequency spectrum of the output from this second sampling circuit 24 and 124 is shown in FIG. This third
As can be seen from the figure, in the frequency spectrum, harmonic components other than the frequency components necessary for the reproduced signal, that is, the audio signal in the case of a CD device, are expressed as follows, assuming that the frequency of the first clock, that is, the sampling frequency is fs. There is only a spectrum centered on frequencies that are integral multiples of 2fs (2, 4, 6, ---), and fs /
The spectrum in the band of 2 to 3 rs/2 is suppressed.

As a result, the low-pass filter 34 connected to the subsequent stage
and 134, those with relatively gentle attenuation characteristics as shown in FIG. 4 can be used. As a low-pass filter having such attenuation characteristics, for example, a third-order Butterworth type low-pass filter as shown in FIG. 5 can be used.

FIG. 6 is a circuit diagram showing another embodiment of the invention. The embodiment shown in FIG. 6 differs from the embodiment shown in FIG. 1 in the configuration of the second sampling circuit. Specifically, in this embodiment, the second sampling circuits 24' and 124' are configured by a low-pass filter 36 and an analog switch 38, and a low-pass filter 136 and an analog switch 38, respectively. Low pass filter 36
and 136 are low-order low-pass filters such as the third-order Butterworth type shown in FIG. 5, respectively. The inputs of these low-pass filters 36 and 136 are directly connected to the outputs of first sampling circuits 14 and 114, respectively. The analog switch 38 shared by the two second sampling circuits 24' and 124' connects the connection point between the first sampling circuit 14 and the low-pass filter 36, and the connection point between the first sampling circuit 114 and the low-pass filter 136. It operates in synchronization with the second clock. The second clock is also selected in this embodiment to be an integral multiple of the frequency of the first clock, preferably an even multiple, for example twice,
When the second clock is high level, analog switch 3
8 connects the output of the first sampling circuit 114 of the right channel to ground, and connects the output of the first sampling circuit 14 of the left channel to ground when the level is low.

Therefore, the analog switch 38 and the low-pass filter 36 constitute a second sampling circuit 24' similar to the embodiment shown in FIG. configured. The outputs of the respective second sampling circuits 24' and 124' are then input to low-pass filters 34 and 134, as in the previous embodiment.

7(A)-(F) are the same as the previous FIG. 2(A)-(E). When the second clock shown in FIG. 7(F) is applied to the analog switch 138, the signals from the second sampling circuits 24' and 124' are
Sampling outputs as shown in FIGS. 7(G) and (H) are obtained. This sampling output is shown in Figure 2 (
Similar to those shown in G) and (H). Therefore, also in the embodiment of FIG. 6, the low-pass filters 34 and 134 (FIG. 1) to be connected at the subsequent stage can be constructed as low-order low-pass filters.

According to the embodiment of FIG. 6, the circuit can be constructed with a simpler circuit than the embodiment of FIG. 1, and specifically, the number of analog switches can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a waveform diagram of each part for explaining the operation of the embodiment of FIG. 1. FIG. 3 is a graph showing the frequency spectrum of the output signal from the second sampling circuit in this embodiment. FIG. 4 is a graph showing an example of the frequency characteristics of a low-pass filter that can be used in this embodiment. FIG. 5 is a circuit diagram showing an example of a low-order low-pass filter that can be used in this embodiment. FIG. 6 is a circuit diagram showing another embodiment of the invention. FIG. 7 is a waveform diagram of each part for explaining the operation of the embodiment shown in FIG. In the figure, 12 and 112 are buffer amplifiers of the DA converter, 14 and 114 are first sampling circuits, and 24 and 1
24. 24', 124' are the second sampling circuits, 3
4.134 indicates a low pass filter. Patent Applicant Sanyo Electric Co., Ltd. Agent Patent Attorney Yama 1) Yoshito (and 1 other person) Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. A DA converter for converting a PCM digital signal into a PAM analog signal; a first DA converter for sampling the output of the DA converter in response to a first clock having a predetermined frequency; a second sampling means for sampling the output of the first sampling means in response to a second clock having a frequency that is an integral multiple of the frequency of the first clock;
and a PCM signal reproducing circuit, comprising a low-pass filter receiving the output of the second sampling means. 2. P according to claim 1, wherein the second clock has a frequency that is an even multiple of the frequency of the first clock.
CM signal reproduction circuit. 3. The PCM digital signal has a plurality of channels, and the DA converter, the first and second sampling means, and the low-pass filter are provided for each channel of the PCM digital signal. The PCM signal reproducing circuit according to item 1 or 2. 4. The second sampling means of each channel is connected to an analog switch that receives the output of the first sampling means and is operated by the second clock, and a hold capacitor that receives the output of the analog switch. 4. A PCM signal reproducing circuit according to claim 3, comprising a buffer amplifier. 5. The PCM digital signal has two channels,
The second sampling means of each channel includes a buffer amplifier that receives the output of the first sampling means of the corresponding channel and is connected to a hold capacitor;
an analog switch connected between the output of the sampling means and the input of the buffer amplifier for alternately connecting the outputs of the first sampling means of the two channels to a reference potential in response to the second clock; Equipped with
A PCM signal reproducing circuit according to claim 3. 6. The PCM signal reproducing circuit according to claim 5, wherein the reference potential is a ground potential.