JPS63126316A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the power consumption effectively with comparatively simple and small-sized constitution by providing a control circuit controlling the operation of a reference voltage generating circuit giving a control voltage to a constant current circuit in an ECL by the control signal. CONSTITUTION:When a storage device is accessed and a chip selection signal, inverse of CS is inputted together with an address signal Ain, a control voltage Vcs is outputted from a reference voltage generating circuit 5, a constant current flows to a constant current circuit IE to bring the ECL 1 to the operating state. When the storage device is in the standby mode, since the signal, inverse of CS is in the inactivated state, the supply of the control voltage Vcs is stopped, no current flows to the circuit IE and most of the operating current of the ECL 1 is cut off immediately. Thus, the power consumption at the in operating time of the ECL1 forming an interface section is suppressed and the entire power consumption of the semiconductor integrated circuit is reduced effectively.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is applicable to semiconductor integrated circuit device technology, and furthermore, to ECL.
This technology is effective when applied to a B i-0 MO3 (bipolar-CMOS composite logic circuit) type semiconductor integrated circuit device that has input/output level compatibility with the B i-0 MO3 (emitter-coupled logic) type. i-CMO
The present invention relates to technology that is effective when used in 5RAM.

[Prior Art] Recently, semiconductor integrated circuit devices have been developed in which only the interface (I/F) section is constructed of ECL, and the internal circuit section is constructed of low power consumption circuits using CMOS or B1-CMOS.

This type of composite semiconductor integrated circuit device is described, for example, in Nikkei Electronics 1986, published by Nikkei McGraw-Hill.
It is attracting attention as "March 10, 2015 issue (Ken 390)" 1.

Here, the present inventor has proposed a Bi-CM to which the above technology is applied.
An O9 type semiconductor memory device was studied. Although the following is not a publicly known technique, it is a technique studied by the present inventor, and its outline is as follows.

Figure 4 shows the B i -CM studied by the present inventor.
1 shows a circuit in a main part of an OS type storage device.

In the B i-CMO3 type O3M shown in the figure, first, an interface (I/F) section that receives external signals such as an address signal Ain is configured by ECLI. This ECLI operates between ground potential and negative power supply VEE,
Predetermined reference voltage ■3. has a logical threshold determined by . Further, the ECLI has a large number of constant current circuits Ia inside thereof. Each constant current circuit Iε is composed of a bipolar transistor QP and a resistor Rε, and by applying a predetermined control voltage Vcs to the base of the bipolar transistor Qε, the control voltage V
A constant current determined by c5 and resistance Rε is applied.

Control voltage VC3 is supplied from a common reference voltage generation circuit 5 provided separately.

The ECL level signal received by the ECLI is converted from the ECL level to the logic level of the CMO 8 by the level conversion circuit 2. The level-converted signal is B i-C
After being logically processed by a decoder 3 comprising an MO3 type O3 circuit 3, a word line driver comprising a Bi-CMO3 type O3 circuit 4 is selectively driven. The selectively driven word line driver drives the word line W from L (low, level) to H (high level), thereby activating the memory cells M in the selected row. The memory cell M is constituted by an MO3 element. Although detailed illustration is omitted, this memory cell M is selected by a word line W wired in the row direction and data lines DI and D2 wired in the column direction.

As mentioned above, while only the interface (1/F) section where signals are exchanged with the outside is configured with ECLI,
Other internal circuits are designed to reduce power consumption i-CM
By configuring with O3 and MOS elements, overall power consumption can be reduced, and ECL and MO
By taking advantage of the respective advantages of S, a high-speed and highly integrated core storage device becomes possible.

[Problems to be Solved by the Invention] However, the inventors have found that the above-mentioned technique has the following problems.

That is, in the above-mentioned B i -CMO9 type storage device, a considerable reduction in power consumption is achieved in the internal circuit section by the Bi-CMO8 and MO3 elements. However, in the ECLI constituting the interface (I/F) section, a large amount of current is constantly flowing through the constant current circuit E etc. inside the ECLI, and therefore a considerable amount of current is consumed. Therefore, even if the power consumption of the internal circuit section is reduced, the power consumption of the interface (I/F) section is still large, so that the overall power consumption is still large.

Therefore, in order to reduce the time-average power consumption of the entire storage device, the present inventors proposed a method of completely shutting off only the operating power of the ECL when the storage device is in a non-selected standby state. A power-down method was considered.

However, this power-down method requires a relatively large-scale power control circuit in order to switch control a large current at high speed. In addition, in the power-down method, since the power is completely cut off once, the start-up of the operation is delayed when switching from non-selected to selected state, and it takes a long time to start up from the power-down state. It has also become clear that another problem arises in that the switching time is longer than the switching time from non-selection to selection.

An object of the present invention is to
It is an object of the present invention to provide a technique for effectively reducing the overall power consumption of a B i-CMO3 type semiconductor integrated circuit device having L with a relatively simple and small-scale configuration.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

In other words, E constituting the interface (I/F) section
The operation of a reference voltage generation circuit that applies a control voltage to the constant current circuit of CL is controlled by a control signal applied from the outside to set a standby mode.

[Operation] According to the above-described means, when in the standby mode, the control voltage that determines the current of the constant current circuit in the ECL is controlled by the control signal that sets the standby mode. As a result, the current flowing through the constant current circuit within the ECL is controlled, and most of the operating current of the ECL is controlled. In this case, the ECL itself remains powered on, so recovery of ECL operation is much faster than recovery from a power-down state.

In this way, for example, without relying on a large-scale power control circuit for switching large currents,
By simply adding a relatively simple and small-scale configuration,
Bi- with ECL in the interface (1/F) part
The objective of effectively reducing the overall power consumption of a CMO3 type O3 body 1fff circuit device is achieved.

[Examples] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

In each figure, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a circuit in a main part of a semiconductor integrated circuit device to which the technology according to the present invention is applied.

The semiconductor integrated circuit device shown in the figure is B i -CM O8
It is configured as a type of static RAM, and first, an interface (
The I/F section is configured by ECLI. This E
CLI operates between ground potential and negative power supply VEE and has a logic threshold determined by a predetermined reference voltage VBB. Further, the FCLI has a large number of constant current circuits Iε inside thereof. Each constant current circuit Iε is composed of a bipolar transistor QE and a resistor RE, and by applying a predetermined control voltage vc5 to the base of the bipolar transistor QE, a constant current determined by the control voltage VC3 and the resistor Rt is generated. flow. The control voltage VC3 is generated by a common reference voltage generation circuit 5 provided separately.
Supplied from.

The ECL level signal received by the ECLI is converted by the level conversion circuit 2 from the BCL level to the CMOS logic level. The level conversion circuit 2 is composed of a MOS (MOS) run lister.

The level-converted signal is logically processed by a decoder 3 consisting of a B1-CMOS logic circuit 3, and then
A word line driver 4 consisting of an i-CMO3 type O3 circuit is selectively driven. B i-CMOS type logic circuit 3.4 is
Its input logic section is composed of CMOS transistors, and its final output stage is composed of bipolar transistors.

The selectively driven word line driver 4 sets the word line W to L.
(low level) to H (high level) to activate the memory cell M in the selected row.The memory cell M is MO3
It is composed of elements (field effect elements). Although detailed illustration is omitted, this memory cell M includes a word line W wired in the row direction and data lines Di, D wired in the column direction.
2 is selected.

As described above, only the interface (I/F) section that exchanges signals with the outside is configured with ECL1, while the other internal circuit sections are configured with low power consumption.
-Constructed of CMOS and MO3 elements.

Here, the B i-CMO3 type O3 tick RAM shown in FIG. 1 is provided with a control circuit 6 for controlling the reference voltage generation circuit 5 in addition to the above-described configuration. This control circuit 6 is operated by a control signal for externally setting the storage device in standby mode, that is, a chip selection signal plane in this case, and the selection signal plane is in an active state (CS="L").
When , the reference voltage generation circuit 5 is operated to output the control voltage V (5), while when the selection signal surface is in the inactive state (="'H"), the operation of the reference voltage generation circuit 5 is controlled. The control voltage VC5 is configured to be cut off by the control voltage VC5.

Next, the operation will be explained.

When the storage device is accessed from the outside, the address signal AL
When the chip selection signal plane is given together with n, the control voltage Vas is generated from the reference voltage generation circuit 5, and this causes a predetermined constant current to flow through the constant current circuit IE in the ECL1, and the ECLI operates. become a state.

On the other hand, when the storage device is not accessed and is in standby mode, the chip selection signal S is in an inactive state (side = "H").
), the supply of the control voltage VCs is stopped, and current no longer flows through the constant current circuit II: in the ECLl.As a result, most of the operating current of the ECLl is transferred with a large time delay. It will be immediately blocked.

In this case, the original operating power of the ECLI remains on, and the control voltage V of the constant current circuit IE in the ECL1 remains on.
ECLI is controlled by ON/OFF control of only c5.
operating current is controlled. By controlling the operating current of an ECLI in this manner, recovery of the ECLI's operation is much faster than recovery from a power-down condition that shuts off the entire operating power supply.

As described above, ECL1, which forms the interface (I/F) section, can be easily controlled by simply adding a relatively simple and small-scale configuration without relying on a large-scale power control circuit for switching large currents. It is possible to suppress current consumption when unnecessary. This makes it possible to effectively reduce the overall power consumption of the semiconductor integrated circuit device.

FIG. 2 shows an embodiment in detail of the reference voltage generating circuit 5 and control circuit 6. In FIG.

In the figure, reference voltage generation circuit 5 includes bipolar transistors Q51. Q52. Resistance R51, R52, R5
3, R54, diodes D51, D52, etc., a constant voltage is divided by diode D51 and bipolar transistor Q51, and this constant voltage is output from bipolar transistor Q52.

The control circuit 6 includes an emitter follower including a bipolar L-run lister Q61 and a constant current circuit I61, and a bipolar transistor Q62. Q63 and constant current circuit I62
It is composed of a differential circuit. The collector of one bipolar transistor Q63 forming this differential circuit is connected within the reference voltage generating circuit 5.

The chip selection signal plane is input to the timing signal generation circuit 7 and also to the control circuit 6.

Chip selection signal surface is active fi (C9="L")
When , the bipolar transistor Q on the differential output side
62 is in an OFF state, and at this time, the reference voltage generating circuit 5 operates normally without receiving interference from the control circuit 6 and outputs a predetermined control voltage VC3.

On the other hand, the chip selection signal plane is inactive M (cs="H")
, that is, when the storage device is in standby mode,
Bipolar transistor Q62 on the differential output side is on.
ON) state. Then, the bipolar l-run lister Q62 in the ON state clamps the voltage divided within the reference voltage generation circuit 5 to the negative side power supply ■εε. As a result, the control voltage Vcs, which is the output of the reference voltage generation circuit 5, is cut off.

FIG. 3 shows another embodiment of the reference voltage generating circuit 5 and control circuit 6. In FIG.

To show only the difference from the one shown in FIG. 2, in this embodiment, the current for dividing the constant voltage in the reference voltage generation circuit 5 is connected to the p-channel MOS 1-run lister M5.
1. The output of the control circuit 6 is input to the gate of this MOS transistor 51.

In the control circuit 6, a pull-up resistor R61 is connected to the collector of the output-side piborar transistor Q63 of the differential circuit. Other than that, it is the same as that shown in FIG.

In this example, the chip select signal plane is in the inactive state (plane =
′”H°゛), the MoS in the reference voltage generation circuit 5
By turning off the transistor 51, the control voltage VC5 is cut off.

Above, the invention made by the present inventor has been specifically explained based on the examples, but it should be noted that the present invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Not even. For example, a portion of peripheral circuits such as a decoder may also be constructed from ECL.

In the above explanation, the invention made by the present inventor was mainly applied to a semiconductor memory device, which is the background field of application. It can also be applied to semiconductor integrated circuit devices having the following functions.

This can be applied at least to conditions that have a standby mode.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, the overall power consumption of a Bi-CMO3 type semiconductor integrated circuit device having an ECL in the interface (I/F) section can be effectively reduced with a relatively simple and small-scale configuration. Effects can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of a circuit in a main part of a semiconductor memory device to which the technology according to the present invention is applied; FIG. 2 is a diagram showing an embodiment of a part of the circuit shown in FIG. 1; FIG. 3 is a diagram showing another embodiment of a part of the circuit shown in FIG. 1, and FIG. 4 is a diagram showing a circuit in the main part of a semiconductor memory device studied prior to the present invention. 1... ECL (which forms the interface (I/F) part)
Emitter coupled logic), It...constant current circuit, VO2
...Control voltage, 2...Level conversion circuit, 3.4--
-Bi-CMO8 type O8 circuit, 5... Reference voltage generation circuit, 6... Control circuit, M... Memory cell, Surface... Chip selection signal (standby mode setting signal). Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. ECL (emitter coupling logic) in the interface section
is formed, a low power consumption type circuit other than ECL is formed in the internal circuit section, and has a standby mode set by an external control signal, wherein the constant current circuit in the ECL has a standby mode set by an external control signal. A semiconductor integrated circuit device comprising a control circuit that controls the operation of a reference voltage generation circuit that provides a control voltage using the control signal. 2. The main part of the internal circuit section is a memory circuit consisting of a memory element constituted by a field effect element and a peripheral circuit constituted by a bipolar CMOS complex logic circuit. semiconductor integrated circuit devices.