JPS631260A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To omit a bypass capacitor and to reduce the size of a camera head by using an emitter follower transistor. CONSTITUTION:An integrated circuit U1 consists of transistors TRQ1-Q4 having emitter follower action and voltage dividing resistances R1-R4. A +16Vin terminal is grounded via an external bypass capacitor CI and therefore the output impedances of a +8Vout terminal, a +7Vout terminal and a +3Vout terminal outputted via the TRQ2-Q4 after division of the voltage of the +16Vin terminal are set at satisfactorily low levels. As a result, conventional bypass capacitors C2-C4 can be omitted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a solid-state imaging device using a solid-state imaging device such as a charge-coupled device (CCD), and particularly relates to a camera head incorporating a solid-state imaging device and a solid-state imaging device. The present invention relates to a solid-state imaging device in which a video processor unit that supplies power supply voltage to a solid-state imaging device and processes signals from a solid-state imaging device is separate.

[Conventional technology]

FIG. 3 shows a conventional example of a solid-state imaging device using an interline transfer type charge-coupled device (COD). The light receiving section of the solid-state image sensor IO consists of photodiodes 1B arranged in a matrix.

Charges generated in the photodiodes 1B in each column (vertical column) are supplied to the vertical transfer CCD 12 via the readout gate 18. The read gate 18 has a read gate terminal LG.
A +3V power supply voltage (DC voltage) is applied through the photodiode 1B, and the charge generated in the photodiode 1B is read out every frame or every field period. Vertical transfer CCD12
are driven by vertical drive pulses φv1, φv2, φv3, φv
This is done by applying a 4-phase lock signal of 4,
The charges generated in the photodiode 16 are read out and transferred at a predetermined timing. The charges transferred within the vertical transfer CCD 12 are supplied to the horizontal transfer CCD 14 for each scanning line.

The horizontal transfer CCD 14 sends out the charges supplied from the vertical transfer CCD 12 one scanning line at a time. Horizontal transfer CC
D14 is driven by horizontal drive pulses φh1, φh2, φh
This is performed by applying a four-phase lock signal of 3 and φh4.

An output gate 20 is formed at the output terminal of the horizontal transfer CCD 14, and a +7v power supply voltage is applied via the output gate terminal OG. The signal charge outputted through this output gate 20 is supplied to the gate of an output transistor 22 made of a field effect transistor (FET), and the signal from each photodiode is transmitted through the source of the output transistor 22 and the signal output terminal v out. An imaging signal corresponding to the charge is output.

A drain voltage of +16V is applied to the drain of the output transistor 22 via the output drain terminal OD.

The source of a reset transistor 24 consisting of an FET is also connected to the gate of the output transistor 22, and after the imaging signal of each photodiode is output, the charge applied to the gate of the output transistor 22 is converted into a reset pulse φ.
The reset transistor 24 is activated at a predetermined timing by R.
It is released from the reset drain terminal RD via the drain of the reset drain terminal RD. A power supply voltage of +18V is also applied to the reset drain terminal RD.

Further, a power supply voltage of Ov is applied to the P well terminal PW of the solid-state image sensor lO, and +8 to the substrate bias terminal SUB.
A power supply voltage of v is applied.

In this way, this solid-state imaging probe 10 requires a total of four types of power supply voltages, and the four types of voltages are connected to a single +16V power supply voltage supplied from the video processor 42 as shown in FIG. It is calculated by dividing the pressure.

The solid-state image sensor 10 is built into a camera head 40, and is connected to a video processor 4 having a power supply circuit, a video signal processing circuit, etc.
2 is connected via a cable line.

The signal output terminal v out of the solid-state image sensor 10 is connected to the base of the output buffer transistor Q1, and the image signal is amplified and output from the emitter. The emitter output of the transistor Ql is connected to the video signal processing circuit (not shown) in the video processor 42 via the inner conductor of the coaxial cable 4B.
transmitted to. The signal processed by the video processor 42 is supplied to a CRT monitor 44 and displayed.

The outer conductor of coaxial cable 46 is grounded within video processor 42 .

+16V from video processor 42 via cable line
A power supply voltage of is applied to the collector of output buffer transistor Q1. A voltage dividing resistor R1 is connected between the collector of the transistor Q1 and the outer conductor (ground) of the coaxial cable 46.
, R2, R3, and R4 are connected in series. Voltage dividing resistor RI
The ratio of the resistance values of SR2, R3, and R4 is set so that the potentials at each voltage dividing point are +8V, +7V, and +3V, respectively.

A +16v voltage terminal (collector of output buffer transistor Ql) is connected to reset drain terminal RD and output drain terminal OD of solid-state image sensor 10. +8v voltage terminal (connection point of resistors R1 and R2) is the solid-state image sensor 10
is connected to the substrate bias terminal SUB. The +7■ voltage terminal (the connection point between resistors R2 and R3) is connected to the output gate terminal OG of the solid-state image sensor 1o. +3v voltage terminal (
The connection point between resistors R3 and R4) is connected to the readout gate terminal LG of the solid-state image sensor 1o. The ground terminal (outer conductor of the coaxial cable 4B) is the P-well terminal p of the solid-state image sensor IO.
connected to w.

In addition, +18V, +8V, +7V, +3Vf17) Each voltage terminal has a bypass capacitor CI.

It is grounded (connected to the outer conductor of the coaxial cable 4B) via C2, C3, and C4. These capacitors ClS
C2, C3, and C4 are for lowering the AC impedance of each voltage terminal, and need to be placed near the solid-state image sensor 10.

[Problem that the invention seeks to solve]

In this way, according to the conventional example, the output buffer transistor Ql and the resistors R1, R2, R3 are provided near the solid-state imaging probe 1o.
, R4, and capacitors CI, C2, C3, and C4. Therefore, even if all of these components were constructed using chip-type components, the total number would be nine, and even if measures such as arranging them on a printed circuit board were taken, this would be an impediment to miniaturizing the camera head. Ta.

This invention was made to deal with the above-mentioned circumstances,
The purpose is to miniaturize the camera head in a solid-state imaging device in which a camera head incorporating a solid-state imaging device and a video processor unit that supplies a power supply voltage to the solid-state imaging device are separate bodies.

[Means for solving problems]

The solid-state imaging device according to the present invention includes a camera head 40 having a solid-state imaging device 10, and a video processor unit 42 that supplies a power supply voltage to the solid-state imaging device 10 and processes signals from the solid-state imaging device 10.
0 are voltage dividing resistors R1, R2, and R3 that generate a plurality of power supply voltages from the power supply voltage supplied from the video processor section 42.
, R4 and emitter follower transistors Q2, Q3,
Equipped with Q4.

[Effect]

According to the solid-state imaging device according to the present invention, a plurality of power supply voltages obtained by dividing a single power supply voltage within the camera head are applied to the solid-state imaging device via the emitter follower transistor, so that each power supply voltage This eliminates the need for a bypass capacitor to lower the AC impedance of the terminals, allowing for a more compact camera head.

〔Example〕

Hereinafter, one embodiment of a solid-state imaging device according to the present invention will be described with reference to the drawings. In this embodiment, an integrated circuit U1 and a capacitor c1 as shown in FIG. 1 are provided in a camera head 40, and are connected to a solid-state image sensor 10 as shown in FIG. The solid-state image sensor 1o utilizes an interline transfer type charge-coupled device (CCD) shown in FIG.

The integrated circuit U1 includes transistors QL, Q2, Q3, and Q4 that operate as emitter followers, and voltage dividing resistors R1 and R2.
, R3, and R4. Transistor Ql is the output buffer transistor Q1 in the conventional example shown in FIG.

The collectors of the transistors Ql, Q2, Q3, and Q4 serve as +18V In terminals, and a power supply voltage of +16V is applied from the video processor 42. The base of the transistor Q1 becomes a V1n terminal, which is connected to the signal output terminal V out of the solid-state image sensor 10. transistor Q
The emitter of 1 is the V out terminal, and the coaxial cable 4
Connected to the inner conductor of 6. The +18V In terminal is grounded (connected to the outer conductor of the coaxial cable 4B) via an external bypass capacitor C1.

Voltage dividing resistors RL, R2, R3, and R4 are connected in series between the +18V In terminal and the GND terminal. Here, the ratio of the resistance values of the voltage dividing resistors differs from the conventional example in that the emitter voltage of the emitter follower transistor to which the voltage at each voltage dividing point is applied to the base is +3V.

It is set to be +7V and +3V.

A connection point between resistors R1 and R2 is connected to the base of transistor Q2. The emitter of transistor Q2 is +13Vo
It becomes the ut terminal and is connected to the substrate bias terminal SUB of the solid-state image sensor 10. A connection point between resistors R2 and R3 is connected to the base of transistor Q3. The emitter of the transistor Q3 becomes the +7■out terminal, and the solid-state image sensor 10
is connected to the output gate terminal OG of. A connection point between resistors R3 and R4 is connected to the base of transistor Q4. The emitter of the transistor Q4 becomes a +3Vout terminal, which is connected to the readout gate terminal LG of the solid-state image sensor IO.

The GND terminal is connected to the P-well terminal PW of the solid-state imaging device 10 and is also grounded within the video processor 42 via the outer conductor of the coaxial cable 46 .

According to this embodiment, since the +18V In terminal is grounded via the external bypass capacitor CI, the voltage at the +18V In terminal is divided and sent via the emitter follower transistors Q2, Q3, and Q4. Output +8Vout#A, +7Vout terminal, +3V
Since the output impedance of the out terminal is sufficiently low, conventional bypass capacitors C2, C3, and C4 are not required. Therefore, it is sufficient to provide only the integrated circuit U1 and the capacitor C1 in the vicinity of the solid-state imaging probe IO. Therefore, the number of parts other than the solid-state image sensor 10 is two, which can be significantly reduced compared to nine in the conventional example, and the camera head can be made smaller.

When this invention is applied to an electronic endoscope with a built-in solid-state image sensor at its tip, its effects will be further enhanced.

Note that the present invention is not limited to the embodiments described above, and can be modified in various ways, and the type of solid-state imaging device, the number of required reference voltages, etc. can be arbitrarily set.

〔Effect of the invention〕

As described above, according to the present invention, by using an emitter follower transistor, it is possible to provide a solid-state imaging device that eliminates the need for a bypass capacitor and can downsize the camera head.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an integrated circuit provided in a camera head of an embodiment of a solid-state imaging device according to the present invention, FIG. 2 is a block diagram of a camera head of an embodiment of a solid-state imaging device, and FIG. FIG. 4 is a block diagram of a conventional example of a solid-state imaging device. 10...Solid-state image sensor Ql, Q2, Q3, Q4...Emitter follower transistor R1, R2, R3, R4...Voltage dividing resistor CI...Bypass capacitor 40...Camera head 42...Video Processor applicant representative Patent attorney Atsushi Tsuboi ND Figure 1, Figure 2v! J

Claims (2)

[Claims] (1) In a solid-state imaging device in which a camera head having a solid-state imaging device and a video processor unit that supplies a power supply voltage to the solid-state imaging device and processes signals from the solid-state imaging device are separate units, the camera head is A means for generating a plurality of power supply voltages from a power supply voltage supplied from the video processor unit, and an emitter follower transistor, and supplying the plurality of power supply voltages to the solid-state image sensor via the emitter follower transistor. Characteristic solid-state imaging device. (2) The solid-state imaging device according to claim 1, wherein the camera head is provided at a distal end of an insertion section of an endoscope.