JPS63122281A - Hetero junction diode and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a hetero junction diode with a high-speed switching characteristic and high breakdown voltage and low series resistance, by forming an n-type layer into a two-layered structure and decreasing the thickness of the n-type layer, in which a junction functioning as a Potential barrier to a hole is formed, in a range where a tunnel effect does not occur. CONSTITUTION:A semiconductor with a large band gap Eg is generally high in resistivity. Therefore, when a diode is composed of such semiconductors as this, a forward voltage drop is enlarged. In order to remove this phenomenon, a n-type layer is formed into such two-layered structure consisting of a n<+> layer 4 and a n<+> layer 5. Namely, when thickness d2 of a region B functioning as a potential barrier to a hole is made smaller than thickness d1 of the n<+> layer 5, a series resistance value of the n-type layer can be decreased. The region B can be made thin to such a degree that a tunnel effect on the hole does not occur, so that even the thickness d2 of 100 nm or less is practically effectual.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a switching diode and a method of manufacturing the same, and more particularly to a heterojunction diode and a method of manufacturing the same.

(Prior art and its problems) A stabilized power supply using a switching regulator is
Although it has become the mainstream of small power supplies, the efficiency of this power supply is greatly influenced by the switching characteristics of the rectifier diodes that make up the main part. In order to improve this switching characteristic, it is desirable that the series resistance be kept low, that the reverse transient current be extremely small, that the breakdown voltage be large, and that high-speed response be possible. The reverse transient current is
A so-called Schottky diode is well known as a diode in which the storage value of injected carriers is small. This Schottky diode utilizes a potential barrier made of a metal-semiconductor junction, and when an n-type semiconductor is used, only electron flow contributes to the rectifying action, so high-speed response is possible. However, since there is a theoretical limit to the height of the potential barrier,
It has the disadvantage that it is difficult to obtain a higher breakdown voltage than a semiconductor pn junction diode.

(Objective of the Invention) An object of the present invention is to provide a structure of a heterojunction diode that has high-speed switching characteristics, high breakdown voltage, and low series resistance, and can realize a highly efficient power supply, and a method for manufacturing the same.

(Features of the Invention 1r1.) The heterojunction diode of the present invention has a basic structure of a junction between an n-type semiconductor with a large band gap and a p-type semiconductor with a smaller band gap. Semiconductors with large band gaps generally have high resistivity. In the heterojunction diode of the present invention, in order to prevent a drop in forward voltage due to high resistivity when a diode is constructed using such a semiconductor, the n-type layer has a two-layer structure, and the diode has a two-layer structure for holes. It is characterized by making the n-type layer forming the junction, which acts as a potential barrier, as thin as possible without creating a tunnel effect.

Further, the dopant of the first n-type layer, that is, the element to which ions are implanted, is the same as the constituent element of the second n-type layer and the constituent element of the underlying substrate. Therefore, the dopant in the first n-type layer is characterized in that it does not act as an impurity on the second n-type layer and the underlying substrate.

Furthermore, since the second n-type layer also functions as a cap layer necessary during annealing after ion implantation, it is characterized in that there is no need to deposit a separate camp layer.

(Principle of the Invention) As shown in FIG. 1(a), the basic structure of the diode of the present invention is as shown in FIG.
p' layer 2p-Si with thickness d4 made of St or p'Ge
or p-layer 3 of thickness d3 made of p-Ge, n''GaP
a first n′ layer of thickness dt consisting of a layer or n′+GaAs layer;
"Layer 4, the second layer of thickness d consisting of n+Si or nGe
1 layer 5 and a negative electrode 6 which is the upper electrode of AI.

FIG. 1(b) is an energy state diagram when no voltage is applied between electrodes 1 and 6, and FIG. 1(C) is an energy state diagram when no voltage is applied between electrodes 1 and 6.
．． 6 is an energy state diagram when a forward voltage is applied between 6 and 6. FIG. The detailed description of the invention below is given for the case of the combination of St and GaP.

i″″GaP″GaP layer 4.1.12e with a bandgap E□ of 2.24 eV, as is clear from
n+SiSi layer 5S with bandgap E, l of V
An i-layer 3 is arranged, an n”GaP IJ4 and a p-Si layer 5
A pn junction is formed at the boundary between the two. In FIG. 1(b), Ef represents the Fermi level, EC represents the energy level at the lower end of the conduction band, and E represents the energy level at the upper end of the valence band. Also, E is the height of the potential barrier to electrons, E
2 is the height of the potential barrier to holes.

Here, when bias voltage 5 is applied between electrodes 1.6, the height of the potential barrier to electrons is E7°=E, -e V, ・------=-, as shown in Figure 1cc).
----------(1) decreases. On the other hand, the height of the potential barrier for holes is E p' −E p e V b −−−−−−−
−・−−−−−−・−−−(2). However, E.
Since the difference between and El is about 1.1 eV, E, 1'
Even if it approaches zero, E,゛ becomes a sufficiently large barrier to holes υ). Therefore, the current flowing through this pn junction contains almost no hole current.

Semiconductors with a large bandgap E generally have high resistivity, so when a diode is constructed of such a semiconductor, the forward voltage drop will be large. In order to eliminate such drawbacks, in the present invention, the n-type layer is replaced with the n-layer 41.
It has a two-layer structure like the three-layer structure 5. That is, Figure Hb
) and (C), the series resistance value of the n-type layer can be reduced by making the thickness d2 of the region B, which acts as a potential barrier for holes, thinner than the thickness dl of the n1 layer 5. B can be made thin to the extent that no tunneling effect occurs for holes, and the thickness dt is
In practice, the effect can be sufficiently obtained even at 100+v or less.

(Structure and operation of the invention) Examples of the present invention will be described below.

(Example 1) FIG. 2(a) shows a first example of a heterojunction diode according to the present invention, in which 1 is an AN positive electrode, 2 is a p-single crystal Si layer, and 3 is a p-single-crystal Si layer. Crystalline Si layer, 4a is 1 single crystal GaP layer, 4b is polycrystalline amorphous GaP layer, 5 is n0 single crystal St layer, 6 is 8E negative electrode, 7 is Si
02 layer and 8 are polycrystalline or amorphous Si layers.

Next, the manufacturing method of this example will be explained.

(2) First step: Using a p-ip"+Si wafer (3, 2) with a (100) plane as a substrate, an insulating layer 7 of SiO□ is formed.

(2) Second Step As shown in FIG. 2(b), the Si01 layer 7 in the portion that will become the active region of the diode is removed and a window is opened to expose a portion of the Si wafer.

(2) Third Step As shown in FIG. 2(C), a non-doped GaP layer (i-GaP) of, for example, 1100 nm is formed on the exposed St and on the 510 g layer 7. Ga on the St screen exposed here
PJ! ! 4C is a single crystal, GaP layer 4 on SiO□
b is polycrystalline or amorphous.

This GaP layer is formed using the MBE method, MO-CVD method (
A sputtering method using Xe ions and polycrystalline GaP (trimethyl gallium and PH1 can be used) or polycrystalline GaP as a target is performed.

■Fourth step As shown in FIG. 2(C), GaP layers 4b and 4c are formed.
A P-doped single crystal Si layer is deposited thereon. The thickness of the Si film is determined to match the performance of the St'" ion implantation device used in the next process, that is, the acceleration energy. For example, when using 200 keV Si", the thickness of the Si film and -The total thickness of GaP N is 0.2 μm
It is necessary to do the following. In this case, the GaP film 4b
The Si film 8 deposited thereon becomes polycrystalline or amorphous.

■Fifth step Next, as shown in Figure 2 (dl), the Si
By performing lamp annealing after ion implantation, the 1-GaP layer in the window region becomes an n'GaP layer 4a in a short time, forming the active region of the diode. Since it is done as a five-cap layer, it has the advantage that there is no need to apply a separate cap layer. -2 A1 layer 5.1 is formed as shown in FIG. 2(e) on the front and back surfaces of the wafer that has been processed from the sixth step up to the fifth step to form an ohmic electrode.

A pn junction diode made by this method is shown in Figure 2.
As is clear from (e), the area around the active region is Si0
It is surrounded by the g layer 7. This SiozlW7
Since it is a stable, high-resistance material, there is no need to add electrical inactivation as a special process.

(Example 2) FIG. 3(a) shows a second example of the present invention, which is manufactured by the following steps.

■First process As shown in Figure 3(b), 1-Ga is added on the p-Si layer 3.
PJ! ! ! 4c is epitaxially grown.

(2) Second step As shown in FIG. 3(b), an insulating layer 7 of Si(h) is formed on the 1-GaP layer 4C.

(3) Third process: Remove the 5102M7 which will become the active region of the diode and open a window to expose a part 4d of the 1-GaP layer 4C.

(4) Fourth Step As shown in FIG. 3(C), a P-doped single crystal Si layer is deposited on the Si02 layer 7 and the exposed 1-GaP layer 4d. In this case, the Si layer 8 deposited on the Si02 film 7
becomes polycrystalline or amorphous.

■Fifth step Next, as shown in Figure 3(d), the Si
By performing lamp annealing after ion implantation, the 1-GaP layer in the window region becomes nGaP@4a in a short time, forming the active region of the diode. .8 as a cap layer has the advantage that there is no need to apply a separate cap layer.

(2) A1 layer 5.1 is formed as shown in FIG. 3(e) on the front and back surfaces of the wafer that has been processed through the sixth step and up to the fifth step to form an ohmic electrode.

A pn junction diode made by this method is shown in Figure 2.
As is clear from (e), the periphery of the active region is 1-G
It is surrounded by the aP layer 4c and the Sift layer 7. Since each of these layers 4c and 7 is a stable high-resistance material, there is no need to add electrical inactivation as a special process.

(Example 3) FIG. 4(a) shows a second example of the present invention, which is manufactured by the following steps.

(1) The first step, (2) the second step, and (2) the third step in the second embodiment can be used as they are. Note that in this embodiment, a resist may be used as the insulating film 7 instead of Si01.

(Fourth step) As shown in FIG. 4(b), SiO! Alternatively, Si ions are implanted using the resist film 7 as a mask.

(Fifth step) Next, remove the Sing or resist insulation Jif7, and
The entire aP layers 4a and 4c are exposed.

(Sixth step) On the fully exposed GaP layers 4a and 4c, a layer shown in FIG.
), P-doped n''51M5 is deposited.

(Seventh step) By performing appropriate annealing, the GaP layer is activated only in the portion where the window was opened as shown in FIG. 4(C).
"A GaP layer 4a is formed. Since the annealing after ion implantation is performed using the n+Si layer 5 as a cap layer, there is an advantage that there is no need to deposit another cap layer.

(Eighth Step) Al electrodes 6.1 are formed on the front and back sides of the wafer that has been processed up to the seventh step, thereby completing the heterojunction diode shown in FIG. 4(a).

(Example 4) Figure 5 (al (bl) (c) is respectively Figure 2 (al
, Examples 1 and 2.3 shown in FIGS. 3(a) and 4(a)
St is replaced with Ge, GaP is replaced with GaAs, Sint is replaced with Si3N4, and P, which is the dopant of the second n-type layer, is replaced with As.
This is Example 4 of the present invention, in which FIG.

Figure 3 (b) (e) (dl (el and Figure 4(b)
(It can be manufactured by applying the same process as described for C1.

(Effects of the Invention) As explained in detail above, in the present invention, nN on the negative molar side is replaced by a material with a large energy gap E (GaP
The following effects (1) and (2) can be obtained by forming a two-layer structure consisting of a small material (St or Ge) and a small amount of E (St or Ge).

■ Since it is a unipolar device in which only electrons contribute to its operation, it can provide the high-speed response required for switching diodes.

■ The effect of reducing the equivalent series resistance can be obtained.

Furthermore, the following effects can be obtained by SP (or Ge'''') ion implantation.

(2) Although the St (or Ge) layer has a doping effect, the GaP (or GaAs) layer can be activated to n' by doping with Si'' (or Ge).

■ For GaP (or GaAs) Ji annealing, S
The t (or Ge) layer acts as a cap layer and allows stable annealing.

(2) Therefore, it is possible to omit the process of forming a cap layer necessary for annealing after ion implantation of the -2 group compound semiconductor into -C.

■ At the junction interface between the n+Si layer and n"GaP ji, the impurity of the n+Si layer is P, and P is also a constituent element of GaP. Therefore, for example, by annealing, the n+
P in GaP near the Si layer is diffused into the n''Si layer, and the n''
- There is no need to worry that GaP near SiN will deviate from its stoichiometry. Therefore, the bonding interface becomes steep, and a good heterojunction interface can be obtained.

[Brief explanation of the drawing]

Figure I Ta) (b) (C1 is an energy state diagram for explaining the structure and operation of the Peter junction diode according to the present invention, Figure 2 (al (b) (C) (d) (e),
Figure 3 (a) (bl ((ri (d) (el), Figure 4 (a) (b) (C1 and Figure 5 (a) (bl
(C) is a sectional view for explaining the manufacturing method according to the present invention. 1... Positive electrode, 2... p+Si (or p"Ge
) N, 3...p-5t (or p-Ge) layer, 4
．． 4a...-n'' GaP (or n'+GaAs) layer, 4
b -SiO on GaP (or GaAs) film
layer, 4c·”1-GaP (or 14aAs) 11!i,
4d-Part of i-GaP (or 1-GaAs) layer 4c, 5-n+Si (or n''Ga) layer, 6... Negative electrode, 7... Insulating layer, 8... Polycrystalline or non-crystalline Crystalline S
i (or Ge) layer. Patent applicant: 1 person other than Shindengen Kogyo Co., Ltd.

Claims (12)

[Claims] (1) By using an n-type semiconductor with a large band gap and a p-type semiconductor with a smaller band gap than the n-type semiconductor, pn
A junction is formed, and the n-type semiconductor has a two-layer structure of a compound semiconductor and an elemental semiconductor, and a tunneling effect occurs in the n-type layer of the compound semiconductor forming the pn junction, which acts as a potential barrier against holes. A heterojunction diode characterized by being formed as thin as possible. (2) The p-type semiconductor is a p^-Si layer, and the n-type semiconductor is composed of n^+GaP and n^+Si layer from the p-type semiconductor.
The heterojunction diode according to claim 1, characterized in that it has a two-layer structure arranged in this order. (3) The p-type semiconductor is a p^-Ge layer, and the n-type semiconductor is composed of n^+GaAs and n^+G from the p-type semiconductor.
The heterojunction diode according to claim 1, characterized in that it has a two-layer structure arranged in the order of e. (4) By using an n-type semiconductor with a large band gap and a p-type semiconductor with a smaller band gap than the n-type semiconductor, pn
A junction is formed, and the n-type semiconductor has a two-layer structure of a first n-type layer made of a compound semiconductor and a second n-type layer made of an elemental semiconductor, and the pn junction acts as a potential barrier against holes. In order to manufacture a heterojunction diode in which the first n-type layer forming the layer is formed thinly within a range that does not cause a tunnel effect, a first step of forming an insulating layer on the p-type semiconductor substrate; By removing a part of the insulating layer and opening a window, the p
a second step of exposing a part of the type semiconductor; and sequentially forming the non-doped compound semiconductor layer and the second n-type layer on the insulating layer and the partially exposed p-type semiconductor. a third step; and a fourth step of implanting ions of a constituent element of the semiconductor of the second n-type layer, which is the single semiconductor, into the non-doped compound semiconductor through the second n-type layer. and a fifth step of activating the compound semiconductor by performing appropriate annealing after the ion implantation. (5) The p-type semiconductor is a p^-Si layer, and the n-type semiconductor is composed of n^+GaP and n^+Si layer from the p-type semiconductor.
5. The method of manufacturing a heterojunction diode according to claim 4, wherein the heterojunction diode has a two-layer structure arranged in this order. (6) The p-type semiconductor is a p^-Ge layer, and the n-type semiconductor is composed of n^+GaAs and n^+G from the p-type semiconductor.
5. The method for manufacturing a heterojunction diode according to claim 4, wherein the heterojunction diode has a two-layer structure arranged in the order of e. (7) By using an n-type semiconductor with a large band gap and a p-type semiconductor with a smaller band gap than the n-type semiconductor, pn
A junction is formed, and the n-type semiconductor has a two-layer structure of a first n-type layer made of a compound semiconductor and a second n-type layer made of an elemental semiconductor, and the pn junction acts as a potential barrier against holes. In order to manufacture a heterojunction diode in which the first n-type layer forming the layer is formed thinly within a range that does not cause a tunnel effect, the first n-type layer forming the non-doped compound semiconductor layer on the p-type semiconductor substrate is a second step of forming an insulating layer on the non-doped compound semiconductor layer; and a second step of forming an insulating layer on the non-doped compound semiconductor layer, and forming a part of the non-doped compound semiconductor layer by removing a part of the insulating layer and opening a window. a third step of exposing the second n-type layer; a fourth step of forming the second n-type layer on the insulating layer and the exposed non-doped compound semiconductor; and a fourth step of forming the second n-type layer on the insulating layer and the exposed non-doped compound semiconductor; A fifth step of ion-implanting constituent elements of the semiconductor of the second n-type layer into the non-doped compound semiconductor layer and performing appropriate annealing to convert only the windowed portion into an n-type active layer. A method of manufacturing a heterojunction diode, comprising: (8) The p-type semiconductor is a p^-Si layer, and the n-type semiconductor is composed of n^+GaP and n^+Si layer from the p-type semiconductor.
8. The method of manufacturing a heterojunction diode according to claim 7, wherein the heterojunction diode has a two-layer structure arranged in this order. (9) The p-type semiconductor is a p^-Ge layer, and the n-type semiconductor is composed of n^+GaAs and n^+G from the p-type semiconductor.
8. The method for manufacturing a heterojunction diode according to claim 7, characterized in that it has a two-layer structure arranged in the order of e. (10) By using an n-type semiconductor with a large band gap and a p-type semiconductor with a smaller band gap than the n-type semiconductor,
An n-junction is formed, and the n-type semiconductor has a two-layer structure of a first n-type layer made of a compound semiconductor and a second n-type layer made of an elemental semiconductor, and the pn junction acts as a potential barrier against holes. In order to manufacture a heterojunction diode in which the first n-type layer forming the junction is formed thinly within a range that does not cause a tunnel effect, the first step is to form the non-doped compound semiconductor layer on the p-type semiconductor substrate. a second step of forming an insulating layer on the non-doped compound semiconductor layer; and a second step of forming an insulating layer on the non-doped first n-type layer by removing a part of the insulating layer and opening a window. a third step of exposing a portion; and a fourth step of implanting ions of a constituent element of the semiconductor of the second n-type layer, which is the single semiconductor, into the exposed non-doped compound semiconductor layer. , a fifth step of removing the insulating layer to fully expose the compound semiconductor layer, a sixth step of forming the second n-type layer on the fully exposed compound semiconductor layer, and a suitable method. a seventh step of activating the compound semiconductor layer in the windowed portion by annealing. (11) The p-type semiconductor is a p^-Si layer, and the n
type semiconductors are n^+GaP and n^+S from the p-type semiconductor.
11. The method for manufacturing a heterojunction diode according to claim 10, wherein the heterojunction diode has a two-layer structure arranged in the order of i. (12) The p-type semiconductor is a p^-Ge layer, and the n
The type semiconductors are n^+GaAs and n^+ from the p-type semiconductor.
11. The method for manufacturing a heterojunction diode according to claim 10, wherein the heterojunction diode has a two-layer structure arranged in the order of Ge.