JPS63120348A - One-chip processor - Google Patents

Abstract

PURPOSE:To decrease the noises produced when an access is given to a memory by having a slight difference between the rise and fall times of an access valid signal applied to each memory module when accesses are simultaneously given to plural memory modules. CONSTITUTION:The instructions stored in a CS 2-1 consisting of plural RAM modules 2 are read out by the addresses stored in an address register 3-1 and set to a register CSDR 3-3. The contents of the CSDR 3-3 are decoded by an instruction decoder 3-4 for control of the inside of a 1-chip processor 1. Then a module address comparator 3-31 compares the module addresses of the register 3-1 and an address +1 circuit 3-30 with each other. When the next access is given to the CS 2-1 with different RAM modules, a dummy FF 3-32 is set. Then the control is carried out so as to cause a slight difference between the rise and fall times of an access valid signal applied to each memory module.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a one-chip processor with a built-in storage device, and particularly to a one-chip processor with a built-in large-capacity storage device.
Regarding processors.

[Conventional technology]

As a prior art related to one-chip processors, for example, the technology described in Japanese Patent Publication No. 10664/1983 is known. This conventional technology is configured so that instructions are externally set via an input/output port and an internal bus in order to perform tests in the manufacturing stage and in the usage stage, and without changing the timing in normal processing. The internal bus can be used for instruction sets.

[Problem that the invention seeks to solve]

However, the above-mentioned conventional technology has the problem that it is not possible to increase the number of power supply bins and ground bins due to limitations associated with single-chip integration, and is susceptible to noise, especially when accessing the built-in storage device. There is a problem in that it is difficult to incorporate a large-capacity storage device due to the problem of noise margin against noise caused by the noise.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above, and to provide a one-chip Bromo 1 storage device that can reduce noise when accessing a storage device and can incorporate a large-capacity storage device.

[Means for solving problems]

According to the present invention, the object is to configure the built-in storage device with a plurality of small capacity storage modules, and to set the access validity No. 13 rising and falling times to be applied to each storage module. During memory module.

This can be achieved by dividing the image into several groups or by controlling each group to be shifted little by little.

[For production]

Generally, CMOS precharge type static RA
A storage module such as M (hereinafter referred to as a RAM module) can be controlled to be accessible by applying an access enable signal,
Noise is generated at the rise and fall of this access valid signal. Therefore, the rise and fall times of the access enable signal applied to each RAM module of a storage device composed of a plurality of small capacity RAM modules are each 17A.
By dividing M module units or into several groups and shifting each group slightly, it is possible to eliminate the overlap of noise that occurs when accessing the storage device, and to reduce the level of generated noise. It can be done.

This makes it possible to configure a one-deep processor that is not affected by noise when accessing the storage device even if it incorporates a large-capacity storage device.

〔Example〕

Hereinafter, one embodiment of the one-chip processor according to the present invention will be described in detail with reference to the drawings.

Fig. 1 is a block diagram showing the entire one-chip network processor, Fig. 2 is a block diagram of the RAM module, and Fig. 3 is a block diagram of the RA module.
M module operation time chart, Figure 4 is a configuration diagram of a control storage device using eight RAM modules, Figure 5 is a diagram showing an example of address conversion circuit, and Figure 6 is a module enable signal generation circuit. FIG. 7 is a time chart thereof, FIG. 8 is a time chart of instruction execution, and FIG. 9 is a configuration diagram of a portion related to instruction execution.

In each figure, 1 is a one-chip processor, 2-chip RA
M module, 3 is an internal arithmetic circuit, 4 is an input/output port, 2-1 is a control storage device, 3-1 is an address register,
3-2 is a module enable signal generation circuit, 3-3
is a read data register, 3-4 is an instruction decoder, 3-
5 is a bank switching circuit, 3-6 is an error module address holding circuit, 3-7 is an address conversion circuit, 3-8 is a check circuit, 3-21 is a decoder, 3-22.3-23 is a flip-flop, 3 -24 is a delay circuit, 3-2
5 is an AND circuit, 3-30 is a +1 circuit, 3-31 is a module address comparison circuit, 3-32 is a dummy flip-flop, and 3-33 is a C8 control circuit.

An embodiment of the one-chip processor 1 according to the present invention includes eight small-capacity RAM modules 2, as shown in FIG.
, RAM, an internal arithmetic circuit 3 containing all logic other than the input/output capo-1, and an input/output port 4 containing the input/output bins of the one-chip processor 1. Small capacity RA
The M module 2 can be configured with, for example, a 128 W x 2 B/W CMOS precharge static RAM, and in the embodiment of the present invention, a 64 W x 4 B/W RAM is used as 128 W x 2 B/W. As a result, the one-chip processor 1 shown in FIG.
The processor has a storage device of . small capacity RAM
As shown in FIG. 2, the module 2 has input of a module enable signal (hereinafter referred to as ME double signal), write/continue control manual R/W, RAM address manual input AO to A5, and data manual input. .

~Di18, data output D0°. ~Constructed with DOI11. The operation of this RAM module 2 is performed according to the time chart 1 shown in FIG.
- ME double signal 1 given while A5' is determined
It is accessed when .

If this access is a read operation, RAM output D0 is obtained by this access. In CMOS precharge type static RAM, as shown in Figure 3, M
Noise occurs at the rise and fall of the E times signal, and its power consumption is large during the period when the ME false signal is "1".
During the period when the ME false signal is "0", it is extremely small.

FIG. 4 shows the configuration of a control storage device (hereinafter referred to as CS) using eight such RAM modules, and C8 includes bank O of RAM modules 2 with module numbers OO to 03, and It consists of two banks, bank 1 consisting of RAM modules 2 numbered 10-13.

Each RAM module 2 receives ME (ME false signals EOO-M2O3, MEIO to ME13 from the i-number generation circuit 3-2).
The access status is controlled individually by In the illustrated embodiment, one RAM module 2 in each bank is controlled so that, for example, RAM modules 2 with module numbers 00, 10.01, 1102, 12JO3, and 13 can be accessed simultaneously, and RAM modules 2 with module numbers 03. RAM module 2 with 13 is connected to other RAM module 2
It is used as a backup in case of failure.

Among the addresses in the address register 3-1, module addresses MAO and MA1 are set to ME as described later.
Given to the signal generation circuit 3-2, ME doubler MEOO~M
The address AO-A5 is used to generate EO3, MEI O-MEI 3, and is given to all RAM modules 2, and becomes the address for the RAM module that is made accessible. The read output D0 of each RAM module 2 is an output Do 00 to Do O3 for each bank.
Not.

~Do13 is input to the bank switching circuit 3-5.

The bank switching circuit 3-5 outputs signals reflecting conditions such as instruction execution results. 00-D003 or Do 10-Do
13 and inputs the selected output to the control storage successive data register (hereinafter referred to as C3DR) 3-3. The instruction decoder 3-4 decodes the data in the C3DR 3-3 and outputs the data in the one-chip processor 1. Execute 111. As mentioned above, the RAM module 2 is 64W x 4B/W or 128W x 2B/W.
Since it is used as W, the 4B readout output read by addresses AO to A5 is divided into 2B by a method not shown and output. Of course, if a 128W x 2B/W RAM module 2 is used, a 2B read output can be obtained directly using a 7-bit address.

The check circuit 3-8 performs a parity check on the data held in the C3DR 3-3, and if an error is detected, it freezes the inside of the one-chip processor 1 by a method not shown and notifies the outside. Report. The error module address holding circuit 3-6 is a circuit that holds the address of the faulty or defective RAM module 2.
For example, it is composed of a 2-bit flip-flop.

The address conversion circuit 3-7 converts the upper two bits of the RAM module address MA0, MA1 in the address register 3-1.
and the faulty RAM module address EAO,1 in the error module address holding circuit 3-6, the RAM module to be actually accessed has address EMA0.
, 1 are generated. The address conversion circuit 3-7 is shown in FIG.
As shown in a), the address EMA0.1 of the RAM module 2 which is actually accessed is determined by the values of MAo, 1 and EAo, 1, as shown in FIG. 5(b). Determine the value. Now all R
If the AM module is normal and RAM module 2 with module number 03.13 is used as a spare,
In the error module address holding circuit 3-6, (11) is held as the address EA0, 1. In this case, module address M of address register 3-1
The value of A0.1 is as shown in the rightmost column of Figure 5 (bl).
All (RAM modules that are actually accessed without being converted are output as EMA0, 1.The check circuit 3-8 reports data errors in the C3DR3-3 to the outside, and the one-deep processor For example, if a failure has occurred in the RAM module with module number 01, the error module address holding circuit 3-6 will have the value (01) as EAO,i stored externally. In this case, the address conversion circuit 3-7 is set as shown in FIG.
) as shown in the center column of address register 3-1.
RAM module address MA0.1 (direct (00
).

(01) and (10) respectively, the value (lO) of the RAM module address EMA0.1 that is actually accessed.
, (11), (00) to make the RAM module with output L7 and module number 01.11 unused.

The RAM module address EMAO11 to be actually accessed outputted from this address conversion circuit 3-7 is M
ME doubler MEO that is applied to the EE signal generation circuit 3-2 and controls a predetermined RAM module 2 to be accessible.
It is used to generate O~MEO3 and MEIO~ME13. FIG. 6 shows the configuration of this MEE signal generation circuit 3-2, which includes a decoder 3-21 that decodes the RAM module address EM'A0.1 to be actually accessed, and a timing pulse TPA.
, Flip-flop 3-22.3 which is set and reset by TPB and controls the ME double signal output time.
-23, ME double trust MEOO~MEO3, MEIO~ME
It is constituted by an AND circuit 3-25 which outputs 13.

Flop/flow viewing tube 3-22 is module number 00
ME double signal EOO for RAM module 2 of ~03
- It determines the time to generate MEO3, and is set by the timing pulse TPA and reset by the timing signal TPB.
23 determines the time for generating ME doublers MEIO to MB13 for the RAM modules 2 with module numbers 10 to 13, and timing pulses TPA, TPB
is set and reset by a pulse delayed by the delay circuit 3-24. AND circuit 3-25 includes flip-flop 122.3-23 and decoder 3-2.
ME doublers ME00 to ME that take the AND of the output signals of 1 and control each RAM module 2 to be accessible.
O3 and MEIO to ME13 are generated and applied to the corresponding RAM module 2.

FIG. 7 shows a time chart of the ME signal generation circuit when the address EMA0.1 given from the address conversion circuit 3-2 is the value (00).

In this case, the MEE signal generation circuit 3-2 generates the ME times signal EO
O and MEIO are set to "1" for a certain period of time determined by timing pulses TPA and TPB, and are applied to the RAM module 2 having the module number 00.10 to make these RAM modules 2 accessible. Furthermore, the ME multiplied signals EOO and MElo are generated with a phase shift of 1 to 2 ns, for example, by a determined time by the delay circuit 3-24. This occurs when the ME double signal rises or falls.
This is to prevent the phases of noise generation from the modules from overlapping, and the delay time of the delay circuit 3-24 is as follows:
It is selected to be as small as possible within a range where the noise of the two RAM modules generated by the ME multiplied signal does not overlap.

This control of the rise and fall of the ME multiplication signal is to prevent the occurrence of malfunctions such as inversion of information in the RAM module and malfunction of the internal arithmetic circuit 3 due to the overlap of this noise and the increase in the noise level. Yes, also RA
This is to ensure that the two RAM modules are simultaneously accessible when the M module 2 is accessed.

Next, the operation of the one-chip processor according to the present invention during instruction execution will be explained with reference to the time chart shown in FIG. 8 and the block diagram related to instruction execution shown in FIG. 9.

C3lI, which is composed of a plurality of RAM modules 2 already explained with reference to FIG.
An internally stored instruction is read by an address within -1 and set in C3DR3-3. C3DR3
The contents of -3 are decoded by the instruction decoder 3-4 and control the inside of the one-chip processor 1. C3 control circuit 3
-33 is set to C32 by the output of the instruction decoder 3-4, etc.
-1, and is a circuit that controls the address register 3-1.
control etc. The address +1 circuit 3-30 performs +1 processing on the address of the address register 3-1, and the next C3
Prepare for reading 2-1. The module address comparison circuit 3-31 compares the module address of the address register 3-1 and the module address of the address +1 circuit 3-30, and determines whether the next access to C52-1 is to the same RAM module 2. It is detected whether or not the access is made, and if the access is to a different RAM module, the dummy flip-flop 3-32 is set. This dummy flip flop O1! /B3-3
When 2 is in the reset state, it means that the same RAM module is accessed, and the CS control circuit 3-33
As shown in FIG. 8, control is performed so that the RAM module is accessed every execution cycle. When the dummy flip controller 7' 3-32 is in the set state, the RAM module to be accessed is switched, and the CS control circuit 3-33 takes two execution cycles to access the RAM module. Take control. CMO
The S precharge type RAM module consumes very little power when the ME multiplication signal is O'', but it has the property that it requires more access time than usual when accessing when restarting. There is a certain RAM in
When switching from accessing a module to accessing another RAM module, a dummy flip
3-32, and performs control to extend access to the RAM module.

As mentioned above, embodiments of the present invention provide a plurality of small-capacity R
By configuring a large-capacity storage device using AM modules and controlling only the small-capacity RAM module necessary for executing instructions so that it can be accessed, it is possible to reduce power consumption in RAM. Furthermore, when making multiple small-capacity RAM modules accessible at the same time, the ME double signals for making them accessible are not applied at the same time, but are applied at a slight shift.
It is possible to prevent overlapping of noises generated by the RAM module at the rise and fall of the ME multiplication signal, and to prevent malfunctions of the one-chip processor due to this noise.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to improve yield and reliability by incorporating a large-capacity storage device that combines multiple small-capacity RAM modules, and to reduce power consumption and noise. We can provide a one-chip processor that solves the problem.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the entire one-chip processor.
Figure 2 is a configuration diagram of a RAM module, Figure 3 is an operation time chart of a RAM module, Figure 4 is a configuration diagram of a control storage device using eight RAM modules, and Figure 5 is an address conversion circuit and an example of address conversion. FIG. 6 is a diagram showing a module enable signal generation circuit, FIG. 7 is a time chart thereof, FIG. 8 is a time chart of instruction execution, and FIG. 9 is a configuration diagram of parts related to instruction execution. be. 1-・-・・−One-chip processor, 2・−・−
・RAM module, 3---internal arithmetic circuit, 4--
-To the crowd capo-I, 2-1-...control storage device, 3-
1---1--address register, 3-2...-
Module enable signal generation circuit, 3-3...
...-Read data register, 3-4--Instruction decoder, 3-5--Bank switching circuit, 3
~6--Error module address holding circuit, 3-7.
-11111 address conversion circuit, 3-8...-check circuit, 3-2 L-----decoder, 3-22.
3-23...--Flip-flop, 3-24-
...-Delay circuit, 3-25--A N D circuit,
3-3 (1--1,000-1 circuit, 3-31--Module address comparison circuit, 3-32--Dummy flip-flop, 3-33--CS Control circuit.Fig. Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 9

Claims (1)

[Claims] 1. In a one-chip processor equipped with a control storage device, an internal arithmetic circuit, an input/output port, etc., the control storage device is composed of a large-capacity storage device that combines a plurality of small-capacity storage modules, and each In order to control the storage modules so that they can be accessed individually, it is possible to independently control the rise and fall times of the access enable signal given to each storage module, and when accessing multiple storage modules simultaneously, the A one-chip processor characterized by controlling the rise and fall times of an access enable signal given to a module so as to be slightly shifted.